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-- Copyright 2007 Actel Corporation. All rights reserved.
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
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-- File: primitives.vhd
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-- Description: CoreFFT
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-- FFT primitives module
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-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
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--
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--
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--------------------------------------------------------------------------------
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-- counts up to TERMCOUNT, then jumps to 0.
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-- Generates tc signal on count==TERMCOUNT-1
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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USE work.fft_components.all;
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ENTITY counter IS
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GENERIC (
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WIDTH : integer := 7;
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TERMCOUNT : integer := 127 );
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PORT (
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clk, nGrst, rst, cntEn : IN std_logic;
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tc : OUT std_logic;
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Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
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END ENTITY counter;
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ARCHITECTURE translated OF counter IS
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SIGNAL tc_out : std_logic;
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SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
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BEGIN
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tc <= tc_out;
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Q <= std_logic_vector(Q_out);
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PROCESS (clk, nGrst)
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BEGIN
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IF (nGrst = '0') THEN
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Q_out <= (OTHERS => '0');
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tc_out <= '0';
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ELSIF (clk'EVENT AND clk = '1') THEN -- nGrst!=0
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IF (rst = '1') THEN
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Q_out <= (OTHERS => '0');
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tc_out <= '0';
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ELSE
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IF (cntEn = '1') THEN -- start cntEn
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tc_out <= to_logic( Q_out = to_unsigned((TERMCOUNT-1),WIDTH));
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IF (Q_out = to_unsigned(TERMCOUNT, WIDTH)) THEN
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Q_out <= (OTHERS => '0');
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ELSE
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Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
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END IF;
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END IF; -- end cntEn
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END IF; -- end rst
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END IF; -- end nGrst
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END PROCESS;
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END ARCHITECTURE translated;
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--------------------------------------------------------------------------
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-- binary counter with no feedback. Counts up to 2^WIDTH - 1
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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ENTITY bcounter IS
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GENERIC (WIDTH : integer:=7 );
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PORT (clk, nGrst, rst, cntEn : IN std_logic;
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Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
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END ENTITY bcounter;
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ARCHITECTURE translated OF bcounter IS
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SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
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BEGIN
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Q <= std_logic_vector(Q_out);
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PROCESS (clk, nGrst)
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BEGIN
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IF (nGrst = '0') THEN
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Q_out <= (OTHERS => '0');
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ELSIF (clk'EVENT AND clk = '1') THEN
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IF (cntEn = '1') THEN
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IF (rst = '1') THEN
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Q_out <= (OTHERS => '0');
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ELSE
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Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END ARCHITECTURE translated;
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--------------------------------------------------------------------------
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-- rising-falling edge detector
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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ENTITY edgeDetect IS
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GENERIC (
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INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
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FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
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PORT (
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clk, clkEn, edgeIn : IN std_logic;
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edgeOut : OUT std_logic);
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END ENTITY edgeDetect;
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ARCHITECTURE translated OF edgeDetect IS
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SIGNAL in_pipe, in_t1 : std_logic; -- regs
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SIGNAL temp_input : std_logic;
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SIGNAL in_w : std_logic;
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SIGNAL temp_output : std_logic;
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SIGNAL out_w : std_logic;
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SIGNAL output_reg : std_logic;
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BEGIN
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edgeOut <= output_reg;
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temp_input <= (in_pipe) WHEN INPIPE /= 0 ELSE edgeIn;
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in_w <= temp_input ;
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temp_output<=
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((NOT in_w) AND in_t1) WHEN FEDGE /= 0 ELSE (in_w AND (NOT in_t1));
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out_w <= temp_output ;
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PROCESS (clk)
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BEGIN
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IF (clk'EVENT AND clk = '1') THEN
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in_pipe <= edgeIn;
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in_t1 <= in_w;
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output_reg <= out_w;
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END IF;
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END PROCESS;
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END ARCHITECTURE translated;
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