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--------------------------------------------------------------------------------
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-- Copyright 2007 Actel Corporation. All rights reserved.
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
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-- File: CoreFFT.vhd
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-- Description: CoreFFT
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-- Top level FFT module
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-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
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-- Notes: FFT In/out pins:
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-- Input | Output | Comments
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-- ------------+------------+------------------
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-- clk | ifoPong |
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-- ifiNreset | |async reset active low
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-- start | |sync reset active high
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-- Load Input data group |
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-- d_im[15:0] | load |when high the inBuf is being loaded
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-- d_re[15:0] | |
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-- d_valid | |
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-- Upload Output data group |
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-- read_y | y_im[15:0] |
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-- | y_re[15:0] |
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-- | y_valid |marks a new output sample)
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-- | y_rdy |when high the results are being uploaded
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE work.fft_components.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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ENTITY CoreFFT IS
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GENERIC (
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LOGPTS : INTEGER := gLOGPTS;
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LOGLOGPTS : INTEGER := gLOGLOGPTS;
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WSIZE : INTEGER := gWSIZE;
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TWIDTH : INTEGER := gTWIDTH;
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DWIDTH : INTEGER := gDWIDTH;
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TDWIDTH : INTEGER := gTDWIDTH;
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RND_MODE : INTEGER := gRND_MODE;
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SCALE_MODE : INTEGER := gSCALE_MODE;
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PTS : INTEGER := gPTS;
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HALFPTS : INTEGER := gHALFPTS;
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inBuf_RWDLY : INTEGER := gInBuf_RWDLY);
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PORT (
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clk : IN STD_LOGIC;
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ifiStart : IN STD_LOGIC; -- start -- cste
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ifiNreset : IN STD_LOGIC;
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ifiD_valid : IN STD_LOGIC; -- d_valid
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ifiRead_y : IN STD_LOGIC; -- read_y
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ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
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ifoLoad : OUT STD_LOGIC; -- load
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ifoPong : OUT STD_LOGIC; -- pong -- UNUSED
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ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
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ifoY_valid : OUT STD_LOGIC; -- y_valid
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ifoY_rdy : OUT STD_LOGIC); -- y_rdy
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END ENTITY CoreFFT;
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ARCHITECTURE translated OF CoreFFT IS
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SIGNAL fft_ongoing : STD_LOGIC;
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SIGNAL fft_done : STD_LOGIC;
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SIGNAL counter : INTEGER;
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SIGNAL counter_out : INTEGER;
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SIGNAL counter_wait : INTEGER;
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SIGNAL fft_ongoing_ok : STD_LOGIC;
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SIGNAL fft_ongoing_ok_1 : STD_LOGIC;
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SIGNAL fft_ongoing_ok_2 : STD_LOGIC;
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SIGNAL fft_ongoing_ok_3 : STD_LOGIC;
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SIGNAL fft_ongoing_ok_4 : STD_LOGIC;
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--
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SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL ren : STD_LOGIC;
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SIGNAL wen : STD_LOGIC;
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--
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SIGNAL ifoLoad_s : STD_LOGIC; -- load
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SIGNAL ifoY_rdy_s : STD_LOGIC; -- y_rdy
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SIGNAL ifoY_rdy_s2 : STD_LOGIC; -- y_rdy
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SIGNAL ifoY_rdy_s3 : STD_LOGIC; -- y_rdy
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SIGNAL ifoY_valid_s : STD_LOGIC; -- y_valid
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SIGNAL ifoPong_s : STD_LOGIC; -- pong -- UNUSED
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SIGNAL ifoPong_first : STD_LOGIC; -- pong -- UNUSED
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-----------------------------------------------------------------------------
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SIGNAL ifoY_im_counter : INTEGER;
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BEGIN
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-----------------------------------------------------------------------------
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-- INPUT INTERFACE
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-----------------------------------------------------------------------------
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-- in ifiD_valid
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-- in (internal) fft_done
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-- out(internal) fft_ongoing
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-- out ifoLoad_s
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PROCESS (clk, ifiNreset)
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BEGIN
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IF ifiNreset = '0' THEN
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counter <= 0;
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fft_ongoing <= '0';
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ifoLoad_s <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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IF fft_ongoing = '0' THEN
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ifoLoad_s <= '1';
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fft_ongoing <= '0';
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IF ifiD_valid = '1' THEN
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ifoLoad_s <= '1';
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IF counter = 255 THEN
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ifoLoad_s <= '0';
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fft_ongoing <= '1';
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counter <= 0;
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ELSE
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counter <= counter + 1;
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END IF;
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END IF;
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ELSIF fft_ongoing_ok = '1' THEN--fft_done
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fft_ongoing <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- WAIT PROCESS
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-----------------------------------------------------------------------------
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PROCESS (clk, ifiNreset)
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BEGIN
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IF ifiNreset = '0' THEN
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-- fft_done <= '0';
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counter_wait <= 0;
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fft_ongoing_ok <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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fft_done <= '0';
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fft_ongoing_ok <= '0';
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IF fft_ongoing = '0' THEN
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-- fft_done <= '1';
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counter_wait <= 1140;--1000;--1140;--855;--936;
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ELSE
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IF counter_wait > 0 THEN
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counter_wait <= counter_wait -1;
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IF counter_wait = 1 THEN
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fft_ongoing_ok <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- OUTPUT INTERFACE
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-----------------------------------------------------------------------------
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PROCESS (clk, ifiNreset)
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BEGIN -- PROCESS
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IF ifiNreset = '0' THEN -- asynchronous reset (active low)
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fft_ongoing_ok_1 <= '0';
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fft_ongoing_ok_2 <= '0';
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fft_ongoing_ok_3 <= '0';
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fft_ongoing_ok_4 <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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fft_ongoing_ok_1 <= fft_ongoing_ok;
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fft_ongoing_ok_2 <= fft_ongoing_ok_1;
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fft_ongoing_ok_3 <= fft_ongoing_ok_2;
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fft_ongoing_ok_4 <= fft_ongoing_ok_3;
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END IF;
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END PROCESS;
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-- in ifiRead_y
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-- in(internal) fft_ongoing_ok
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-- out (internal) fft_done
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-- out ifoY_im
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-- out ifoY_re
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-- out ifoY_valid_s
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-- out ifoY_rdy_s
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PROCESS (clk, ifiNreset)
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BEGIN
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IF ifiNreset = '0' THEN
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-- fft_done <= '0';
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--ifoY_im <= (OTHERS => '0');
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--ifoY_re <= (OTHERS => '0');
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ifoY_valid_s <= '0';
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ifoY_rdy_s <= '0';
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counter_out <= 0;
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ELSIF clk'EVENT AND clk = '1' THEN
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-- fft_done <= '0';
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IF fft_ongoing_ok_4 = '1' THEN
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counter_out <= 256;
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END IF;
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ifoY_valid_s <= '0';
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ifoY_rdy_s <= '0';
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IF counter_out > 0 THEN
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ifoY_valid_s <= '1';
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ifoY_rdy_s <= '1';
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IF ifiRead_y = '1' THEN
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counter_out <= counter_out - 1;
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--IF counter_out = 1 THEN
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-- fft_done <= '1';
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--END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- DATA
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-----------------------------------------------------------------------------
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lpp_fifo_1: lpp_fifo
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GENERIC MAP (
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tech => 0,
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Mem_use => use_CEL,
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DataSz => 32,
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AddrSz => 7)
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PORT MAP (
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clk => clk,
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rstn => ifiNreset,
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ReUse => '0',
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wen => wen,
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wdata => wdata,
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ren => ren,
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rdata => rdata,
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empty => OPEN,
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full => OPEN,
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almost_full => OPEN);
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wen <= '0' WHEN ifoLoad_s = '1' AND ifiD_valid = '1' ELSE '1';
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wdata <= ifiD_im & ifiD_re;
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ren <= '0' WHEN ifoY_rdy_s = '1' AND ifiRead_y = '1' ELSE '1';
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ifoY_im <= STD_LOGIC_VECTOR(to_unsigned(ifoY_im_counter,16));--rdata(31 DOWNTO 16);
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ifoY_re <= rdata(15 DOWNTO 0);
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PROCESS (clk, ifiNreset)
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BEGIN
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IF ifiNreset = '0' THEN
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ifoY_im_counter <= 0;
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ELSIF clk'event AND clk = '1' THEN
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IF ifoY_rdy_s = '1' AND ifiRead_y = '1' THEN
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ifoY_im_counter <= ifoY_im_counter + 1;
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END IF;
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END IF;
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END PROCESS;
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ifoLoad <= ifoLoad_s;
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ifoY_rdy <= ifoY_rdy_s OR ifoY_rdy_s2 OR ifoY_rdy_s3;
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PROCESS (clk, ifiNreset)
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BEGIN
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IF ifiNreset = '0' THEN
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ifoY_valid <= '0';
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ifoY_rdy_s2 <= '0';
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ifoY_rdy_s3 <= '0';
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ifoPong_s <= '0';
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ifoPong_first <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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ifoY_valid <= ifoY_valid_s;
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ifoY_rdy_s2 <= ifoY_rdy_s;
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ifoY_rdy_s3 <= ifoY_rdy_s2;
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IF fft_ongoing_ok = '1' THEN
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IF ifoPong_first = '1' THEN
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ifoPong_s <= NOT ifoPong_s;
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END IF;
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ifoPong_first <= '1';
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END IF;
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END IF;
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END PROCESS;
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ifoPong <= ifoPong_s;
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END ARCHITECTURE translated;
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