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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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use lpp.general_purpose.all;
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--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
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entity FilterCTRLR is
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port(
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reset : in std_logic;
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clk : in std_logic;
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sample_clk : in std_logic;
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ALU_Ctrl : out std_logic_vector(3 downto 0);
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sample_in : in samplT;
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coef : out std_logic_vector(Coef_SZ-1 downto 0);
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sample : out std_logic_vector(Smpl_SZ-1 downto 0)
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);
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end FilterCTRLR;
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architecture ar_FilterCTRLR of FilterCTRLR is
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constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
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constant DENCoefsCnt : integer:= DenominatorCoefs'high;
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signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
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signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
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signal chanelCnt : integer range 0 to 15:=0;
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signal WD : std_logic_vector(35 downto 0);
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signal WD_D : std_logic_vector(35 downto 0);
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signal RD : std_logic_vector(35 downto 0);
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signal WEN, REN,WEN_D : std_logic;
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signal WADDR_back : std_logic_vector(7 downto 0);
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signal ADDR : std_logic_vector(7 downto 0);
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signal ADDR_D : std_logic_vector(7 downto 0);
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signal clk_inv : std_logic;
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type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
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signal in_Rotate_Buff : Rotate_BuffT;
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signal out_Rotate_Buff : Rotate_BuffT;
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signal sample_clk_old : std_logic;
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type stateT is (waiting,computeNUM,computeDEN,NextChanel);
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signal state : stateT;
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begin
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clk_inv <= not clk;
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process(clk,reset)
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begin
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if reset = '0' then
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state <= waiting;
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WEN <= '1';
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REN <= '1';
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ADDR <= (others => '0');
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WD <= (others => '0');
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NcoefCnt <= 0;
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DcoefCnt <= 0;
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chanelCnt <= 0;
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ALU_Ctrl <= clr_mac;
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sample_clk_old <= '0';
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coef <= (others => '0');
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sample <= (others => '0');
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rst:for i in 0 to ChanelsCNT-1 loop
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in_Rotate_Buff(i) <= (others => '0');
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end loop;
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elsif clk'event and clk = '1' then
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sample_clk_old <= sample_clk;
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--=================================================================
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--===============DATA processing===================================
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--=================================================================
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case state is
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when waiting=>
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if sample_clk_old = '0' and sample_clk = '1' then
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ALU_Ctrl <= MAC_op;
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sample <= in_Rotate_Buff(0);
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coef <= std_logic_vector(NumeratorCoefs(0));
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else
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ALU_Ctrl <= clr_mac;
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loadinput: for i in 0 to ChanelsCNT-1 loop
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in_Rotate_Buff(i) <= sample_in(i);
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end loop;
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end if;
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when computeNUM=>
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ALU_Ctrl <= MAC_op;
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sample <= RD(Smpl_SZ-1 downto 0);
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coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
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when computeDEN=>
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ALU_Ctrl <= MAC_op;
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sample <= RD(Smpl_SZ-1 downto 0);
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coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
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when NextChanel=>
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rotate : for i in 0 to ChanelsCNT-2 loop
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in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
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end loop;
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rotatetoo: if ChanelsCNT > 1 then
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sample <= in_Rotate_Buff(1);
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coef <= std_logic_vector(NumeratorCoefs(0));
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end if;
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end case;
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--=================================================================
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--===============RAM read write====================================
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--=================================================================
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case state is
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when waiting=>
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if sample_clk_old = '0' and sample_clk = '1' then
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REN <= '0';
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else
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REN <= '1';
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end if;
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ADDR <= (others => '0');
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WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
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WEN <= '1';
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when computeNUM=>
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WD <= RD;
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REN <= '0';
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WEN <= '0';
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ADDR <= std_logic_vector(unsigned(ADDR)+1);
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when computeDEN=>
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WD <= RD;
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REN <= '0';
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WEN <= '0';
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ADDR <= std_logic_vector(unsigned(ADDR)+1);
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when NextChanel=>
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REN <= '1';
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WEN <= '1';
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end case;
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--=================================================================
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--=================================================================
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--===============FSM Management====================================
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--=================================================================
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case state is
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when waiting=>
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if sample_clk_old = '0' and sample_clk = '1' then
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state <= computeNUM;
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end if;
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DcoefCnt <= 0;
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NcoefCnt <= 1;
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chanelCnt<= 0;
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when computeNUM=>
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if NcoefCnt = NumCoefsCnt then
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state <= computeDEN;
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NcoefCnt <= 1;
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else
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NcoefCnt <= NcoefCnt+1;
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end if;
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when computeDEN=>
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if DcoefCnt = DENCoefsCnt then
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state <= NextChanel;
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DcoefCnt <= 0;
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else
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DcoefCnt <= DcoefCnt+1;
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end if;
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when NextChanel=>
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if chanelCnt = (ChanelsCNT-1) then
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state <= waiting;
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else
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chanelCnt<= chanelCnt+1;
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state <= computeNUM;
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end if;
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end case;
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--=================================================================
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end if;
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end process;
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ADDRreg : REG
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generic map(size => 8)
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port map(
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reset => reset,
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clk => clk,
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D => ADDR,
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Q => ADDR_D
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);
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WDreg :REG
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generic map(size => 36)
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port map(
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reset => reset,
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clk => clk,
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D => WD,
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Q => WD_D
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);
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WRreg :REG
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generic map(size => 1)
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port map(
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reset => reset,
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clk => clk,
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D(0) => WEN,
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Q(0) => WEN_D
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);
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--==============================================================
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--=========================R A M================================
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--==============================================================
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memRAM : if Mem_use = use_RAM generate
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RAMblk :RAM
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port map(
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WD => WD_D,
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RD => RD,
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WEN => WEN_D,
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REN => REN,
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WADDR => ADDR_D,
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RADDR => ADDR,
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RWCLK => clk_inv,
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RESET => reset
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) ;
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end generate;
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memCEL : if Mem_use = use_CEL generate
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RAMblk :RAM
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port map(
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WD => WD_D,
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RD => RD,
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WEN => WEN_D,
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REN => REN,
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WADDR => ADDR_D,
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RADDR => ADDR,
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RWCLK => clk_inv,
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RESET => reset
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) ;
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end generate;
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--==============================================================
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end ar_FilterCTRLR;
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