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added back IIR filter
jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -
r83:850e54f169a0 alexis
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.iir_filter.all;
31 use lpp.general_purpose.all;
32 use lpp.lpp_amba.all;
33 use lpp.apb_devices_list.all;
34
35 entity APB_IIR_CEL is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Sample_SZ : integer := 16;
43 ChanelsCount : integer := 1;
44 Coef_SZ : integer := 9;
45 CoefCntPerCel: integer := 3;
46 Cels_count : integer := 5;
47 virgPos : integer := 3;
48 Mem_use : integer := use_RAM
49 );
50 port (
51 rst : in std_logic;
52 clk : in std_logic;
53 apbi : in apb_slv_in_type;
54 apbo : out apb_slv_out_type;
55 sample_clk : in std_logic;
56 sample_clk_out : out std_logic;
57 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
58 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
59 );
60 end;
61
62
63 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
64
65 constant REVISION : integer := 1;
66
67 constant pconfig : apb_config_type := (
68 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
69 1 => apb_iobar(paddr, pmask));
70
71
72
73 type FILTERreg is record
74 regin : in_IIR_CEL_reg;
75 regout : out_IIR_CEL_reg;
76 end record;
77
78 signal Rdata : std_logic_vector(31 downto 0);
79 signal r : FILTERreg;
80 signal filter_reset : std_logic:='0';
81 signal smp_cnt : integer :=0;
82 signal sample_clk_out_R : std_logic;
83
84
85 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
86 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
87
88 type CoefsRegT is record
89 numCoefs : CoefTblT;
90 denCoefs : CoefTblT;
91 end record;
92
93 signal CoefsReg : CoefsRegT;
94
95 begin
96
97 filter_reset <= rst and r.regin.config(0);
98 sample_clk_out <= sample_clk_out_R;
99
100 filter : IIR_CEL_FILTER
101 generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
102 port map(
103 reset => filter_reset,
104 clk => clk,
105 sample_clk => sample_clk,
106 regs_in => r.regin,
107 regs_out => r.regout,
108 sample_in => sample_in,
109 sample_out => sample_out
110 );
111
112 process(rst,sample_clk)
113 begin
114 if rst = '0' then
115 smp_cnt <= 0;
116 sample_clk_out_R <= '0';
117 elsif sample_clk'event and sample_clk = '1' then
118 if smp_cnt = 1 then
119 smp_cnt <= 0;
120 sample_clk_out_R <= not sample_clk_out_R;
121 else
122 smp_cnt <= smp_cnt +1;
123 end if;
124 end if;
125 end process;
126
127
128 process(rst,clk)
129 begin
130 if rst = '0' then
131 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
132
133 elsif clk'event and clk = '1' then
134
135
136 --APB Write OP
137 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
138 case apbi.paddr(7 downto 2) is
139 when "000000" =>
140 r.regin.config(0) <= apbi.pwdata(0);
141 when "000001" =>
142 r.regin.virgPos <= apbi.pwdata(4 downto 0);
143 when others =>
144 for i in 0 to Cels_count-1 loop
145 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
146 case apbi.paddr(4 downto 2) is
147 when "000" =>
148 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
149 when "001" =>
150 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
151 when "010" =>
152 CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
153 when "011" =>
154 CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
155 when "100" =>
156 CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
157 when "101" =>
158 CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
159 when others =>
160 end case;
161 end if;
162 end loop;
163 end case;
164 end if;
165
166 --APB READ OP
167 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
168 case apbi.paddr(7 downto 2) is
169 when "000000" =>
170
171 when "000001" =>
172 Rdata(4 downto 0) <= r.regin.virgPos;
173 when others =>
174 for i in 0 to Cels_count-1 loop
175 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
176 case apbi.paddr(4 downto 2) is
177 when "000" =>
178 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0));
179 when "001" =>
180 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1));
181 when "010" =>
182 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2));
183 when "011" =>
184 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0));
185 when "100" =>
186 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1));
187 when "101" =>
188 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2));
189 when others =>
190 end case;
191 end if;
192 end loop;
193 end case;
194 end if;
195
196 end if;
197 apbo.pconfig <= pconfig;
198 end process;
199
200 apbo.prdata <= Rdata when apbi.penable = '1' ;
201
202 -- pragma translate_off
203 bootmsg : report_version
204 generic map ("apbuart" & tost(pindex) &
205 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
206 ", irq " & tost(pirq));
207 -- pragma translate_on
208
209
210
211 end ar_APB_IIR_CEL;
212
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
30 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
31 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
32
33 entity FILTER is
34 generic(Smpl_SZ : integer := 16;
35 ChanelsCNT : integer := 3
36 );
37 port(
38
39 reset : in std_logic;
40 clk : in std_logic;
41 sample_clk : in std_logic;
42 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
43 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
44 );
45 end entity;
46
47
48
49
50
51 architecture ar_FILTER of FILTER is
52
53
54
55
56 signal ALU_ctrl : std_logic_vector(3 downto 0);
57 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
58 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
59 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
60
61 begin
62
63 --==============================================================
64 --=========================A L U================================
65 --==============================================================
66 ALU1 : entity ALU
67 generic map(
68 Arith_en => 1,
69 Logic_en => 0,
70 Input_SZ_1 => Smpl_SZ,
71 Input_SZ_2 => Coef_SZ
72
73 )
74 port map(
75 clk => clk,
76 reset => reset,
77 ctrl => ALU_ctrl,
78 OP1 => Sample,
79 OP2 => Coef,
80 RES => ALU_OUT
81 );
82 --==============================================================
83
84 --==============================================================
85 --===============F I L T E R C O N T R O L E R================
86 --==============================================================
87 filterctrlr1 : FilterCTRLR
88 port map(
89 reset => reset,
90 clk => clk,
91 sample_clk => sample_clk,
92 ALU_Ctrl => ALU_ctrl,
93 sample_in => sample_Tbl,
94 coef => Coef,
95 sample => Sample
96 );
97 --==============================================================
98
99 chanelCut : for i in 0 to ChanelsCNT-1 generate
100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
101 end generate;
102
103
104
105
106 end ar_FILTER;
107
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29
30 --TODO am�liorer la flexibilit� de la config de la RAM.
31
32 entity FILTER_RAM_CTRLR is
33 port(
34 reset : in std_logic;
35 clk : in std_logic;
36 run : in std_logic;
37 GO_0 : in std_logic;
38 B_A : in std_logic;
39 writeForce : in std_logic;
40 next_blk : in std_logic;
41 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
42 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
43 );
44 end FILTER_RAM_CTRLR;
45
46
47 architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
48
49 signal WD : std_logic_vector(35 downto 0);
50 signal WD_D : std_logic_vector(35 downto 0);
51 signal RD : std_logic_vector(35 downto 0);
52 signal WEN, REN : std_logic;
53 signal WADDR_back : std_logic_vector(7 downto 0);
54 signal WADDR_back_D: std_logic_vector(7 downto 0);
55 signal RADDR : std_logic_vector(7 downto 0);
56 signal WADDR : std_logic_vector(7 downto 0);
57 signal WADDR_D : std_logic_vector(7 downto 0);
58 signal run_D : std_logic;
59 signal run_D_inv : std_logic;
60 signal run_inv : std_logic;
61 signal next_blk_D : std_logic;
62 signal MUX2_inst1_sel : std_logic;
63
64
65 begin
66
67 sample_out <= RD(Smpl_SZ-1 downto 0);
68
69 MUX2_inst1_sel <= run_D and not next_blk;
70 run_D_inv <= not run_D;
71 run_inv <= not run;
72 WEN <= run_D_inv and not writeForce;
73 REN <= run_inv ;--and not next_blk;
74
75
76 --==============================================================
77 --=========================R A M================================
78 --==============================================================
79 memRAM : if Mem_use = use_RAM generate
80 RAMblk :RAM
81 port map(
82 WD => WD_D,
83 RD => RD,
84 WEN => WEN,
85 REN => REN,
86 WADDR => WADDR,
87 RADDR => RADDR,
88 RWCLK => clk,
89 RESET => reset
90 ) ;
91 end generate;
92
93 memCEL : if Mem_use = use_CEL generate
94 RAMblk :RAM_CEL
95 port map(
96 WD => WD_D,
97 RD => RD,
98 WEN => WEN,
99 REN => REN,
100 WADDR => WADDR,
101 RADDR => RADDR,
102 RWCLK => clk,
103 RESET => reset
104 ) ;
105 end generate;
106 --==============================================================
107 --==============================================================
108
109
110 ADDRcntr_inst : ADDRcntr
111 port map(
112 clk => clk,
113 reset => reset,
114 count => run,
115 clr => GO_0,
116 Q => RADDR
117 );
118
119
120
121 MUX2_inst1 :MUX2
122 generic map(Input_SZ => Smpl_SZ)
123 port map(
124 sel => MUX2_inst1_sel,
125 IN1 => sample_in,
126 IN2 => RD(Smpl_SZ-1 downto 0),
127 RES => WD(Smpl_SZ-1 downto 0)
128 );
129
130
131 MUX2_inst2 :MUX2
132 generic map(Input_SZ => 8)
133 port map(
134 sel => next_blk_D,
135 IN1 => WADDR_D,
136 IN2 => WADDR_back_D,
137 RES => WADDR
138 );
139
140
141 next_blkRreg :REG
142 generic map(size => 1)
143 port map(
144 reset => reset,
145 clk => clk,
146 D(0) => next_blk,
147 Q(0) => next_blk_D
148 );
149
150 WADDR_backreg :REG
151 generic map(size => 8)
152 port map(
153 reset => reset,
154 clk => B_A,
155 D => RADDR,
156 Q => WADDR_back
157 );
158
159 WADDR_backreg2 :REG
160 generic map(size => 8)
161 port map(
162 reset => reset,
163 clk => B_A,
164 D => WADDR_back,
165 Q => WADDR_back_D
166 );
167
168 WDRreg :REG
169 generic map(size => Smpl_SZ)
170 port map(
171 reset => reset,
172 clk => clk,
173 D => WD(Smpl_SZ-1 downto 0),
174 Q => WD_D(Smpl_SZ-1 downto 0)
175 );
176
177 RunRreg :REG
178 generic map(size => 1)
179 port map(
180 reset => reset,
181 clk => clk,
182 D(0) => run,
183 Q(0) => run_D
184 );
185
186
187
188 ADDRreg :REG
189 generic map(size => 8)
190 port map(
191 reset => reset,
192 clk => clk,
193 D => RADDR,
194 Q => WADDR_D
195 );
196
197
198
199 end ar_FILTER_RAM_CTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26
27 package FILTERcfg is
28
29
30
31
32 --===========================================================|
33 --========F I L T E R C O N F I G V A L U E S=============|
34 --===========================================================|
35 --____________________________
36 --Bus Width and chanels number|
37 --____________________________|
38 constant ChanelsCNT : integer := 6;
39 constant Smpl_SZ : integer := 16;
40 constant Coef_SZ : integer := 9;
41 constant Scalefac_SZ: integer := 3;
42 constant Cels_count : integer := 5;
43
44 constant Mem_use : integer := 1;
45
46
47
48 --============================================================
49 -- create each initial values for each coefs ============
50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 --============================================================
52 --constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
53 --constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
54 --constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
55 --constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
56 --constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
57 --constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
58 --constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
59 --
60 --constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
61 --constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
62 --constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
63 --constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
64 --constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
65 --
66 --
67 --constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
68 --constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
69 --constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
70 --
71 --constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
72 --constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
73 --constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
74 --
75 --constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
76 --constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
77 --constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
78 --
79 --constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
80 --constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
81 --constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
82 --
83 --constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
84 --constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
85 --constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
86 --
87 --constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
88 --constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
89 --constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
90 --
91 --constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
92 --constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
93 --constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
94 --
95 --
96 --constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
97 --constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
98 --constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
99 --
100 --constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
101 --constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
102 --constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
103 --
104 --constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
105 --constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
106 --constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
107 --
108 --constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
109 --constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
110 --constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
111 --
112 --constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
113 --constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
114 --constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
115 --
116 --constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
117 --constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
118 --constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
119 --constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
120 --constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
121 --constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
122 --
123 --
124 --constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
125 --constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
126 --constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
127 --constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
128 --constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
129 --constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
130 --constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
131 --
132 --constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
133 --constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
134 --constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
135 --constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
136 --constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
137 --constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
138 --constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
139 --
140 --
141 --
142 --constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
143 --constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
144 --constant virgPos : integer := 7;
145 --
146 --
147 --
148 --
149 --
150 --
151 --
152 --signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
153 --signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
154 --
155 --
156 --signal sample_Tbl : samplT;
157
158
159 end;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29
30 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
31
32 entity FilterCTRLR is
33 port(
34 reset : in std_logic;
35 clk : in std_logic;
36 sample_clk : in std_logic;
37 ALU_Ctrl : out std_logic_vector(3 downto 0);
38 sample_in : in samplT;
39 coef : out std_logic_vector(Coef_SZ-1 downto 0);
40 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
41 );
42 end FilterCTRLR;
43
44
45 architecture ar_FilterCTRLR of FilterCTRLR is
46
47 constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
48 constant DENCoefsCnt : integer:= DenominatorCoefs'high;
49
50 signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
51 signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
52
53 signal chanelCnt : integer range 0 to 15:=0;
54
55 signal WD : std_logic_vector(35 downto 0);
56 signal WD_D : std_logic_vector(35 downto 0);
57 signal RD : std_logic_vector(35 downto 0);
58 signal WEN, REN,WEN_D : std_logic;
59 signal WADDR_back : std_logic_vector(7 downto 0);
60 signal ADDR : std_logic_vector(7 downto 0);
61 signal ADDR_D : std_logic_vector(7 downto 0);
62 signal clk_inv : std_logic;
63
64 type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
65 signal in_Rotate_Buff : Rotate_BuffT;
66 signal out_Rotate_Buff : Rotate_BuffT;
67
68 signal sample_clk_old : std_logic;
69
70 type stateT is (waiting,computeNUM,computeDEN,NextChanel);
71 signal state : stateT;
72
73 begin
74 clk_inv <= not clk;
75
76 process(clk,reset)
77 begin
78 if reset = '0' then
79 state <= waiting;
80 WEN <= '1';
81 REN <= '1';
82 ADDR <= (others => '0');
83 WD <= (others => '0');
84 NcoefCnt <= 0;
85 DcoefCnt <= 0;
86 chanelCnt <= 0;
87 ALU_Ctrl <= clr_mac;
88 sample_clk_old <= '0';
89 coef <= (others => '0');
90 sample <= (others => '0');
91 rst:for i in 0 to ChanelsCNT-1 loop
92 in_Rotate_Buff(i) <= (others => '0');
93 end loop;
94 elsif clk'event and clk = '1' then
95
96 sample_clk_old <= sample_clk;
97
98 --=================================================================
99 --===============DATA processing===================================
100 --=================================================================
101 case state is
102 when waiting=>
103
104 if sample_clk_old = '0' and sample_clk = '1' then
105 ALU_Ctrl <= MAC_op;
106 sample <= in_Rotate_Buff(0);
107 coef <= std_logic_vector(NumeratorCoefs(0));
108 else
109 ALU_Ctrl <= clr_mac;
110 loadinput: for i in 0 to ChanelsCNT-1 loop
111 in_Rotate_Buff(i) <= sample_in(i);
112 end loop;
113 end if;
114
115 when computeNUM=>
116 ALU_Ctrl <= MAC_op;
117 sample <= RD(Smpl_SZ-1 downto 0);
118 coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
119
120 when computeDEN=>
121 ALU_Ctrl <= MAC_op;
122 sample <= RD(Smpl_SZ-1 downto 0);
123 coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
124
125 when NextChanel=>
126 rotate : for i in 0 to ChanelsCNT-2 loop
127 in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
128 end loop;
129 rotatetoo: if ChanelsCNT > 1 then
130 sample <= in_Rotate_Buff(1);
131 coef <= std_logic_vector(NumeratorCoefs(0));
132 end if;
133 end case;
134
135 --=================================================================
136 --===============RAM read write====================================
137 --=================================================================
138 case state is
139 when waiting=>
140 if sample_clk_old = '0' and sample_clk = '1' then
141 REN <= '0';
142 else
143 REN <= '1';
144 end if;
145 ADDR <= (others => '0');
146 WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
147 WEN <= '1';
148
149 when computeNUM=>
150 WD <= RD;
151 REN <= '0';
152 WEN <= '0';
153 ADDR <= std_logic_vector(unsigned(ADDR)+1);
154 when computeDEN=>
155 WD <= RD;
156 REN <= '0';
157 WEN <= '0';
158 ADDR <= std_logic_vector(unsigned(ADDR)+1);
159 when NextChanel=>
160 REN <= '1';
161 WEN <= '1';
162 end case;
163 --=================================================================
164
165
166 --=================================================================
167 --===============FSM Management====================================
168 --=================================================================
169 case state is
170 when waiting=>
171 if sample_clk_old = '0' and sample_clk = '1' then
172 state <= computeNUM;
173 end if;
174 DcoefCnt <= 0;
175 NcoefCnt <= 1;
176 chanelCnt<= 0;
177 when computeNUM=>
178 if NcoefCnt = NumCoefsCnt then
179 state <= computeDEN;
180 NcoefCnt <= 1;
181 else
182 NcoefCnt <= NcoefCnt+1;
183 end if;
184 when computeDEN=>
185 if DcoefCnt = DENCoefsCnt then
186 state <= NextChanel;
187 DcoefCnt <= 0;
188 else
189 DcoefCnt <= DcoefCnt+1;
190 end if;
191 when NextChanel=>
192 if chanelCnt = (ChanelsCNT-1) then
193 state <= waiting;
194 else
195 chanelCnt<= chanelCnt+1;
196 state <= computeNUM;
197 end if;
198 end case;
199 --=================================================================
200
201 end if;
202 end process;
203
204 ADDRreg : REG
205 generic map(size => 8)
206 port map(
207 reset => reset,
208 clk => clk,
209 D => ADDR,
210 Q => ADDR_D
211 );
212
213 WDreg :REG
214 generic map(size => 36)
215 port map(
216 reset => reset,
217 clk => clk,
218 D => WD,
219 Q => WD_D
220 );
221
222 WRreg :REG
223 generic map(size => 1)
224 port map(
225 reset => reset,
226 clk => clk,
227 D(0) => WEN,
228 Q(0) => WEN_D
229 );
230 --==============================================================
231 --=========================R A M================================
232 --==============================================================
233 memRAM : if Mem_use = use_RAM generate
234 RAMblk :RAM
235 port map(
236 WD => WD_D,
237 RD => RD,
238 WEN => WEN_D,
239 REN => REN,
240 WADDR => ADDR_D,
241 RADDR => ADDR,
242 RWCLK => clk_inv,
243 RESET => reset
244 ) ;
245 end generate;
246
247 memCEL : if Mem_use = use_CEL generate
248 RAMblk :RAM
249 port map(
250 WD => WD_D,
251 RD => RD,
252 WEN => WEN_D,
253 REN => REN,
254 WADDR => ADDR_D,
255 RADDR => ADDR,
256 RWCLK => clk_inv,
257 RESET => reset
258 ) ;
259 end generate;
260
261 --==============================================================
262
263
264
265 end ar_FilterCTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 library IEEE;
24 use IEEE.numeric_std.all;
25 use IEEE.std_logic_1164.all;
26 library lpp;
27 use lpp.iir_filter.all;
28 use lpp.general_purpose.all;
29
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31
32 entity IIR_CEL_CTRLR is
33 generic(Sample_SZ : integer := 16;
34 ChanelsCount : integer := 1;
35 Coef_SZ : integer := 9;
36 CoefCntPerCel: integer := 3;
37 Cels_count : integer := 5;
38 Mem_use : integer := use_RAM
39 );
40 port(
41 reset : in std_logic;
42 clk : in std_logic;
43 sample_clk : in std_logic;
44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 virg_pos : in integer;
47 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
48 );
49 end IIR_CEL_CTRLR;
50
51
52
53
54 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
55
56 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
57
58 signal smpl_clk_old : std_logic := '0';
59 signal WD_sel : std_logic := '0';
60 signal Read : std_logic := '0';
61 signal SVG_ADDR : std_logic := '0';
62 signal count : std_logic := '0';
63 signal Write : std_logic := '0';
64 signal WADDR_sel : std_logic := '0';
65 signal GO_0 : std_logic := '0';
66
67 signal RAM_sample_in : sampleVect;
68 signal RAM_sample_in_bk: sampleVect;
69 signal RAM_sample_out : sampleVect;
70 signal ALU_ctrl : std_logic_vector(3 downto 0);
71 signal ALU_sample_in : sampleVect;
72 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
73 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
74 signal curentCel : integer range 0 to Cels_count-1 := 0;
75 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
76
77
78 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
79
80 signal sample_in_BUFF : sampleBuffT;
81 signal sample_out_BUFF : sampleBuffT;
82
83 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
84 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
85
86 type CoefsRegT is record
87 numCoefs : CoefTblT;
88 denCoefs : CoefTblT;
89 end record;
90
91 signal CoefsReg : CoefsRegT;
92
93 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
94
95 signal IIR_CEL_STATE : fsmIIR_CEL_T;
96
97 begin
98
99
100 coefsConnectL0: for z in 0 to Cels_count-1 generate
101 coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate
102 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
103 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
104 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 end generate;
106 end generate;
107 end generate;
108
109
110 RAM_CTRLR2inst : RAM_CTRLR2
111 generic map(Sample_SZ,Mem_use)
112 port map(
113 reset => reset,
114 clk => clk,
115 WD_sel => WD_sel,
116 Read => Read,
117 WADDR_sel => WADDR_sel,
118 count => count,
119 SVG_ADDR => SVG_ADDR,
120 Write => Write,
121 GO_0 => GO_0,
122 sample_in => RAM_sample_in,
123 sample_out => RAM_sample_out
124 );
125
126
127
128 ALU_inst :ALU
129 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
130 port map(
131 clk => clk,
132 reset => reset,
133 ctrl => ALU_ctrl,
134 OP1 => ALU_sample_in,
135 OP2 => ALU_coef_in,
136 RES => ALU_out
137 );
138
139
140
141
142
143
144 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
145 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
146 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
147 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
148 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
149 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
150 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
151
152 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
153
154
155
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157
158
159
160 process(clk,reset)
161 variable result : std_logic_vector(Sample_SZ-1 downto 0);
162
163 begin
164
165 if reset = '0' then
166
167 smpl_clk_old <= '0';
168 RAM_sample_in <= (others=> '0');
169 ALU_ctrl <= IDLE;
170 ALU_sample_in <= (others=> '0');
171 ALU_Coef_in <= (others=> '0');
172 RAM_sample_in_bk<= (others=> '0');
173 curentCel <= 0;
174 curentChan <= 0;
175 IIR_CEL_STATE <= waiting;
176 resetL0 : for i in 0 to ChanelsCount-1 loop
177 sample_in_BUFF(i) <= (others => '0');
178 sample_out_BUFF(i) <= (others => '0');
179 resetL1: for j in 0 to Sample_SZ-1 loop
180 sample_out(i,j) <= '0';
181 end loop;
182 end loop;
183
184 elsif clk'event and clk = '1' then
185
186 smpl_clk_old <= sample_clk;
187
188 case IIR_CEL_STATE is
189
190 when waiting =>
191 if sample_clk = '1' and smpl_clk_old = '0' then
192 IIR_CEL_STATE <= pipe1;
193 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
194 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
195
196 else
197 ALU_ctrl <= IDLE;
198 smplConnectL0: for i in 0 to ChanelsCount-1 loop
199 smplConnectL1: for j in 0 to Sample_SZ-1 loop
200 sample_in_BUFF(i)(j) <= sample_in(i,j);
201 sample_out(i,j) <= sample_out_BUFF(i)(j);
202 end loop;
203 end loop;
204 end if;
205 curentCel <= 0;
206 curentChan <= 0;
207
208 when pipe1 =>
209 IIR_CEL_STATE <= computeb1;
210 ALU_ctrl <= MAC_op;
211 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
212
213 when computeb1 =>
214
215 ALU_ctrl <= MAC_op;
216 ALU_sample_in <= RAM_sample_out;
217 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
218 IIR_CEL_STATE <= computeb2;
219 RAM_sample_in <= RAM_sample_in_bk;
220 when computeb2 =>
221 ALU_sample_in <= RAM_sample_out;
222 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
223 IIR_CEL_STATE <= computea1;
224
225
226 when computea1 =>
227 ALU_sample_in <= RAM_sample_out;
228 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
229 IIR_CEL_STATE <= computea2;
230
231
232 when computea2 =>
233 ALU_sample_in <= RAM_sample_out;
234 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
235 IIR_CEL_STATE <= next_cel;
236
237
238 when next_cel =>
239 ALU_ctrl <= clr_mac;
240 IIR_CEL_STATE <= pipe2;
241
242 when pipe2 =>
243 IIR_CEL_STATE <= pipe3;
244
245
246 when pipe3 =>
247
248 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
249
250 sample_out_BUFF(0) <= result;
251 RAM_sample_in_bk <= result;
252 RAM_sample_in <= result;
253 if curentCel = Cels_count-1 then
254 IIR_CEL_STATE <= next_chan;
255 curentCel <= 0;
256 else
257 curentCel <= curentCel + 1;
258 IIR_CEL_STATE <= pipe1;
259 ALU_sample_in <= result;
260 end if;
261 when next_chan =>
262
263 rotate : for i in 1 to ChanelsCount-1 loop
264 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
265 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
266 end loop;
267 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
268 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
269
270 if curentChan = (ChanelsCount-1) then
271 IIR_CEL_STATE <= waiting;
272 ALU_ctrl <= clr_mac;
273 elsif ChanelsCount>1 then
274 curentChan <= curentChan + 1;
275 IIR_CEL_STATE <= pipe1;
276 ALU_sample_in <= sample_in_BUFF(1);
277 RAM_sample_in <= sample_in_BUFF(1);
278 end if;
279 end case;
280
281 end if;
282 end process;
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288
289 end ar_IIR_CEL_CTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.general_purpose.all;
28
29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30
31 entity IIR_CEL_FILTER is
32 generic(Sample_SZ : integer := 16;
33 ChanelsCount : integer := 1;
34 Coef_SZ : integer := 9;
35 CoefCntPerCel: integer := 3;
36 Cels_count : integer := 5;
37 Mem_use : integer := use_RAM);
38 port(
39 reset : in std_logic;
40 clk : in std_logic;
41 sample_clk : in std_logic;
42 regs_in : in in_IIR_CEL_reg;
43 regs_out : in out_IIR_CEL_reg;
44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
47
48 );
49 end IIR_CEL_FILTER;
50
51
52
53
54 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
55
56 signal virg_pos : integer;
57 begin
58
59 virg_pos <= to_integer(unsigned(regs_in.virgPos));
60
61 CTRLR : IIR_CEL_CTRLR
62 generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
63 port map(
64 reset => reset,
65 clk => clk,
66 sample_clk => sample_clk,
67 sample_in => sample_in,
68 sample_out => sample_out,
69 virg_pos => virg_pos,
70 coefs => coefs
71 );
72
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74
75
76
77 end ar_IIR_CEL_FILTER;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM;
33
34
35 architecture DEF_ARCH of RAM is
36 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
37 signal RAMarray : RAMarrayT:=(others => X"000000000");
38 signal RD_int : std_logic_vector(35 downto 0);
39
40 begin
41
42 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
43
44
45 process(RWclk,reset)
46 begin
47 if reset = '0' then
48 RD <= (X"000000000");
49 rst:for i in 0 to 255 loop
50 RAMarray(i) <= (others => '0');
51 end loop;
52
53 elsif RWclk'event and RWclk = '1' then
54 if REN = '0' then
55 RD <= RD_int;
56 end if;
57
58 if WEN = '0' then
59 RAMarray(to_integer(unsigned(WADDR))) <= WD;
60 end if;
61
62 end if;
63 end process;
64 end DEF_ARCH;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM_CEL;
33
34
35
36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"000000000");
39 signal RD_int : std_logic_vector(35 downto 0);
40
41 begin
42
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44
45
46 process(RWclk,reset)
47 begin
48 if reset = '0' then
49 RD <= (X"000000000");
50 rst:for i in 0 to 255 loop
51 RAMarray(i) <= (others => '0');
52 end loop;
53
54 elsif RWclk'event and RWclk = '1' then
55 if REN = '0' then
56 RD <= RD_int;
57 end if;
58
59 if WEN = '0' then
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 end if;
62
63 end if;
64 end process;
65 end ar_RAM_CEL;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29
30 --TODO amliorer la flexibilit de la config de la RAM.
31
32 entity RAM_CTRLR2 is
33 generic(
34 Input_SZ_1 : integer := 16;
35 Mem_use : integer := use_RAM
36 );
37 port(
38 reset : in std_logic;
39 clk : in std_logic;
40 WD_sel : in std_logic;
41 Read : in std_logic;
42 WADDR_sel : in std_logic;
43 count : in std_logic;
44 SVG_ADDR : in std_logic;
45 Write : in std_logic;
46 GO_0 : in std_logic;
47 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
48 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
49 );
50 end RAM_CTRLR2;
51
52
53 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
54
55 signal WD : std_logic_vector(35 downto 0);
56 signal WD_D : std_logic_vector(35 downto 0);
57 signal RD : std_logic_vector(35 downto 0);
58 signal WEN, REN : std_logic;
59 signal WADDR_back : std_logic_vector(7 downto 0);
60 signal WADDR_back_D: std_logic_vector(7 downto 0);
61 signal RADDR : std_logic_vector(7 downto 0);
62 signal WADDR : std_logic_vector(7 downto 0);
63 signal WADDR_D : std_logic_vector(7 downto 0);
64
65
66
67 begin
68
69 sample_out <= RD(Input_SZ_1-1 downto 0);
70
71
72 WEN <= not Write;
73 REN <= not read;
74
75
76 --==============================================================
77 --=========================R A M================================
78 --==============================================================
79 memRAM : if Mem_use = use_RAM generate
80 RAMblk :RAM
81 port map(
82 WD => WD_D,
83 RD => RD,
84 WEN => WEN,
85 REN => REN,
86 WADDR => WADDR,
87 RADDR => RADDR,
88 RWCLK => clk,
89 RESET => reset
90 ) ;
91 end generate;
92
93 memCEL : if Mem_use = use_CEL generate
94 RAMblk :RAM_CEL
95 port map(
96 WD => WD_D,
97 RD => RD,
98 WEN => WEN,
99 REN => REN,
100 WADDR => WADDR,
101 RADDR => RADDR,
102 RWCLK => clk,
103 RESET => reset
104 ) ;
105 end generate;
106 --==============================================================
107 --==============================================================
108
109
110 ADDRcntr_inst : ADDRcntr
111 port map(
112 clk => clk,
113 reset => reset,
114 count => count,
115 clr => GO_0,
116 Q => RADDR
117 );
118
119
120
121 MUX2_inst1 :MUX2
122 generic map(Input_SZ => Input_SZ_1)
123 port map(
124 sel => WD_sel,
125 IN1 => sample_in,
126 IN2 => RD(Input_SZ_1-1 downto 0),
127 RES => WD(Input_SZ_1-1 downto 0)
128 );
129
130
131 MUX2_inst2 :MUX2
132 generic map(Input_SZ => 8)
133 port map(
134 sel => WADDR_sel,
135 IN1 => WADDR_D,
136 IN2 => WADDR_back_D,
137 RES => WADDR
138 );
139
140
141
142
143 WADDR_backreg :REG
144 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
145 port map(
146 reset => reset,
147 clk => SVG_ADDR,
148 D => RADDR,
149 Q => WADDR_back
150 );
151
152 WADDR_backreg2 :REG
153 generic map(size => 8)
154 port map(
155 reset => reset,
156 clk => SVG_ADDR,
157 D => WADDR_back,
158 Q => WADDR_back_D
159 );
160
161 WDRreg :REG
162 generic map(size => Input_SZ_1)
163 port map(
164 reset => reset,
165 clk => clk,
166 D => WD(Input_SZ_1-1 downto 0),
167 Q => WD_D(Input_SZ_1-1 downto 0)
168 );
169
170
171
172
173 ADDRreg :REG
174 generic map(size => 8)
175 port map(
176 reset => reset,
177 clk => clk,
178 D => RADDR,
179 Q => WADDR_D
180 );
181
182
183
184 end ar_RAM_CTRLR2;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26
27
28 entity TestbenshMAC is
29 end TestbenshMAC;
30
31
32
33
34 architecture ar_TestbenshMAC of TestbenshMAC is
35
36
37
38 constant OP1sz : integer := 16;
39 constant OP2sz : integer := 12;
40 --IDLE =00 MAC =01 MULT =10 ADD =11
41 constant IDLE : std_logic_vector(1 downto 0) := "00";
42 constant MAC : std_logic_vector(1 downto 0) := "01";
43 constant MULT : std_logic_vector(1 downto 0) := "10";
44 constant ADD : std_logic_vector(1 downto 0) := "11";
45
46 signal clk : std_logic:='0';
47 signal reset : std_logic:='0';
48 signal clrMAC : std_logic:='0';
49 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
50 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
51 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
52 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
53
54
55
56
57 begin
58
59
60 MAC1 : entity LPP_IIR_FILTER.MAC
61 generic map(
62 Input_SZ_A => OP1sz,
63 Input_SZ_B => OP2sz
64
65 )
66 port map(
67 clk => clk,
68 reset => reset,
69 clr_MAC => clrMAC,
70 MAC_MUL_ADD => MAC_MUL_ADD,
71 OP1 => Operand1,
72 OP2 => Operand2,
73 RES => Resultat
74 );
75
76 clk <= not clk after 25 ns;
77
78 process
79 begin
80 wait for 40 ns;
81 reset <= '1';
82 wait for 11 ns;
83 Operand1 <= X"0001";
84 Operand2 <= X"001";
85 MAC_MUL_ADD <= ADD;
86 wait for 50 ns;
87 Operand1 <= X"0001";
88 Operand2 <= X"100";
89 wait for 50 ns;
90 Operand1 <= X"0001";
91 Operand2 <= X"001";
92 MAC_MUL_ADD <= MULT;
93 wait for 50 ns;
94 Operand1 <= X"0002";
95 Operand2 <= X"002";
96 wait for 50 ns;
97 clrMAC <= '1';
98 wait for 50 ns;
99 clrMAC <= '0';
100 Operand1 <= X"0001";
101 Operand2 <= X"003";
102 MAC_MUL_ADD <= MAC;
103 wait;
104 end process;
105 end ar_TestbenshMAC;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29
30
31
32
33 package iir_filter is
34
35
36 --===========================================================|
37 --================A L U C O N T R O L======================|
38 --===========================================================|
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44
45 --____
46 --RAM |
47 --____|
48 constant use_RAM : integer := 1;
49 constant use_CEL : integer := 0;
50
51
52 --===========================================================|
53 --=============C O E F S ====================================|
54 --===========================================================|
55 -- create a specific type of data for coefs to avoid errors |
56 --===========================================================|
57
58 type scaleValT is array(natural range <>) of integer;
59
60 type samplT is array(natural range <>,natural range <>) of std_logic;
61
62 type in_IIR_CEL_reg is record
63 config : std_logic_vector(31 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
65 end record;
66
67 type out_IIR_CEL_reg is record
68 config : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
70 end record;
71
72
73
74 component APB_IIR_CEL is
75 generic (
76 pindex : integer := 0;
77 paddr : integer := 0;
78 pmask : integer := 16#fff#;
79 pirq : integer := 0;
80 abits : integer := 8;
81 Sample_SZ : integer := 16;
82 ChanelsCount : integer := 1;
83 Coef_SZ : integer := 9;
84 CoefCntPerCel: integer := 3;
85 Cels_count : integer := 5;
86 virgPos : integer := 3;
87 Mem_use : integer := use_RAM
88 );
89 port (
90 rst : in std_logic;
91 clk : in std_logic;
92 apbi : in apb_slv_in_type;
93 apbo : out apb_slv_out_type;
94 sample_clk : in std_logic;
95 sample_clk_out : out std_logic;
96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
98 );
99 end component;
100
101
102 --component FILTER is
103 --generic(Smpl_SZ : integer := 16;
104 -- ChanelsCNT : integer := 3
105 --);
106 --port(
107 --
108 -- reset : in std_logic;
109 -- clk : in std_logic;
110 -- sample_clk : in std_logic;
111 -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
112 -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
113 --);
114 --end component;
115
116
117
118 --component FilterCTRLR is
119 --port(
120 -- reset : in std_logic;
121 -- clk : in std_logic;
122 -- sample_clk : in std_logic;
123 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
124 -- sample_in : in samplT;
125 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
126 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
127 --);
128 --end component;
129
130
131 --component FILTER_RAM_CTRLR is
132 --port(
133 -- reset : in std_logic;
134 -- clk : in std_logic;
135 -- run : in std_logic;
136 -- GO_0 : in std_logic;
137 -- B_A : in std_logic;
138 -- writeForce : in std_logic;
139 -- next_blk : in std_logic;
140 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
141 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
142 --);
143 --end component;
144
145
146 component IIR_CEL_CTRLR is
147 generic(Sample_SZ : integer := 16;
148 ChanelsCount : integer := 1;
149 Coef_SZ : integer := 9;
150 CoefCntPerCel: integer := 3;
151 Cels_count : integer := 5;
152 Mem_use : integer := use_RAM
153 );
154 port(
155 reset : in std_logic;
156 clk : in std_logic;
157 sample_clk : in std_logic;
158 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
159 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
160 virg_pos : in integer;
161 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
162 );
163 end component;
164
165
166 component RAM is
167 port( WD : in std_logic_vector(35 downto 0); RD : out
168 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
169 WADDR : in std_logic_vector(7 downto 0); RADDR : in
170 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
171 ) ;
172 end component;
173
174
175 component RAM_CEL is
176 port( WD : in std_logic_vector(35 downto 0); RD : out
177 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
178 WADDR : in std_logic_vector(7 downto 0); RADDR : in
179 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
180 ) ;
181 end component;
182
183 component IIR_CEL_FILTER is
184 generic(Sample_SZ : integer := 16;
185 ChanelsCount : integer := 1;
186 Coef_SZ : integer := 9;
187 CoefCntPerCel: integer := 3;
188 Cels_count : integer := 5;
189 Mem_use : integer := use_RAM);
190 port(
191 reset : in std_logic;
192 clk : in std_logic;
193 sample_clk : in std_logic;
194 regs_in : in in_IIR_CEL_reg;
195 regs_out : in out_IIR_CEL_reg;
196 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
197 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
198 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
199
200 );
201 end component;
202
203
204 component RAM_CTRLR2 is
205 generic(
206 Input_SZ_1 : integer := 16;
207 Mem_use : integer := use_RAM
208 );
209 port(
210 reset : in std_logic;
211 clk : in std_logic;
212 WD_sel : in std_logic;
213 Read : in std_logic;
214 WADDR_sel : in std_logic;
215 count : in std_logic;
216 SVG_ADDR : in std_logic;
217 Write : in std_logic;
218 GO_0 : in std_logic;
219 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
220 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
221 );
222 end component;
223
224
225 end;
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1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
4 FILTERcfg.vhd
5 FilterCTRLR.vhd
6 IIR_CEL_CTRLR.vhd
7 IIR_CEL_FILTER.vhd
8 RAM.vhd
9 RAM_CEL.vhd
10 RAM_CTRLR2.vhd
11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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