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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL; -- PLE
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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USE work.config.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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ENTITY MINI_LFR_top IS
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PORT (
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clk_50 : IN STD_LOGIC;
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clk_49 : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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--BPs
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BP0 : IN STD_LOGIC;
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BP1 : IN STD_LOGIC;
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--LEDs
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LED0 : OUT STD_LOGIC;
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LED1 : OUT STD_LOGIC;
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LED2 : OUT STD_LOGIC;
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--UARTs
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TXD1 : IN STD_LOGIC;
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RXD1 : OUT STD_LOGIC;
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nCTS1 : OUT STD_LOGIC;
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nRTS1 : IN STD_LOGIC;
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TXD2 : IN STD_LOGIC;
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RXD2 : OUT STD_LOGIC;
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nCTS2 : OUT STD_LOGIC;
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nDTR2 : IN STD_LOGIC;
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nRTS2 : IN STD_LOGIC;
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nDCD2 : OUT STD_LOGIC;
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--EXT CONNECTOR
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IO0 : INOUT STD_LOGIC;
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IO1 : INOUT STD_LOGIC;
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IO2 : INOUT STD_LOGIC;
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IO3 : INOUT STD_LOGIC;
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IO4 : INOUT STD_LOGIC;
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IO5 : INOUT STD_LOGIC;
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IO6 : INOUT STD_LOGIC;
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IO7 : INOUT STD_LOGIC;
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IO8 : INOUT STD_LOGIC;
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IO9 : INOUT STD_LOGIC;
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IO10 : INOUT STD_LOGIC;
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IO11 : INOUT STD_LOGIC;
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--SPACE WIRE
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SPW_EN : OUT STD_LOGIC; -- 0 => off
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SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
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SPW_NOM_SIN : IN STD_LOGIC;
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SPW_NOM_DOUT : OUT STD_LOGIC;
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SPW_NOM_SOUT : OUT STD_LOGIC;
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SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
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SPW_RED_SIN : IN STD_LOGIC;
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SPW_RED_DOUT : OUT STD_LOGIC;
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SPW_RED_SOUT : OUT STD_LOGIC;
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-- MINI LFR ADC INPUTS
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ADC_nCS : OUT STD_LOGIC;
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ADC_CLK : OUT STD_LOGIC;
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ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- SRAM
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SRAM_nWE : OUT STD_LOGIC;
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SRAM_CE : OUT STD_LOGIC;
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SRAM_nOE : OUT STD_LOGIC;
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SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END MINI_LFR_top;
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ARCHITECTURE beh OF MINI_LFR_top IS
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COMPONENT leon3_soc
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GENERIC (
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fabtech : INTEGER;
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memtech : INTEGER;
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padtech : INTEGER;
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clktech : INTEGER;
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disas : INTEGER;
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dbguart : INTEGER;
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pclow : INTEGER);
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PORT (
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clk100MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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errorn : OUT STD_ULOGIC;
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ahbrxd : IN STD_ULOGIC;
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ahbtxd : OUT STD_ULOGIC;
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urxd1 : IN STD_ULOGIC;
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utxd1 : OUT STD_ULOGIC;
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address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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spw1_din : IN STD_LOGIC;
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spw1_sin : IN STD_LOGIC;
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spw1_dout : OUT STD_LOGIC;
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spw1_sout : OUT STD_LOGIC;
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spw2_din : IN STD_LOGIC;
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spw2_sin : IN STD_LOGIC;
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spw2_dout : OUT STD_LOGIC;
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spw2_sout : OUT STD_LOGIC;
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apbi_wfp : OUT apb_slv_in_type;
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apbo_wfp : IN apb_slv_out_type;
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ahbi_wfp : OUT AHB_Mst_In_Type;
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ahbo_wfp : IN AHB_Mst_Out_Type;
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
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END COMPONENT;
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BEGIN -- beh
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PROCESS (clk_50, reset)
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BEGIN -- PROCESS
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IF reset = '0' THEN -- asynchronous reset (active low)
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LED0 <= '0';
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LED1 <= '0';
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LED2 <= '0';
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ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
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LED0 <= '0';
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LED1 <= '1';
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LED2 <= BP0;
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END IF;
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END PROCESS;
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--UARTs
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RXD1 <= '0';
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nCTS1 <= '0';
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RXD2 <= '0';
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nCTS2 <= '0';
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nDCD2 <= '0';
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--EXT CONNECTOR
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IO0 <= clk_49;
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IO1 <= clk_50;
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IO2 <= SPW_NOM_DIN OR
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SPW_NOM_SIN OR
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SPW_RED_DIN OR
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SPW_RED_SIN;
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IO3 <= ADC_SDO(0);
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IO4 <= ADC_SDO(1);
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IO5 <= ADC_SDO(2);
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IO6 <= ADC_SDO(3);
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IO7 <= ADC_SDO(4);
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IO8 <= ADC_SDO(5);
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IO9 <= ADC_SDO(6);
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IO10 <= ADC_SDO(7);
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IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
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--SPACE WIRE
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SPW_EN <= '0'; -- 0 => off
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SPW_NOM_DOUT <= '0';
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SPW_NOM_SOUT <= '0';
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SPW_RED_DOUT <= '0';
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SPW_RED_SOUT <= '0';
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ADC_nCS <= '0';
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ADC_CLK <= '0';
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-- SRAM
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SRAM_nWE <= '1';
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SRAM_CE <= '0';
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SRAM_nOE <= '1';
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SRAM_nBE <= (OTHERS => '1');
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SRAM_A <= (OTHERS => '0');
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SRAM_DQ <= (OTHERS => '0');
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leon3mp_1: leon3_soc
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GENERIC MAP (
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fabtech => fabtech,
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memtech => memtech,
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padtech => padtech,
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clktech => clktech,
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disas => disas,
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dbguart => dbguart,
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pclow => pclow)
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PORT MAP (
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clk100MHz => clk100MHz,
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clk49_152MHz => clk49_152MHz,
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reset => reset,
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errorn => errorn,
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ahbrxd => ahbrxd,
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ahbtxd => ahbtxd,
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urxd1 => urxd1,
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utxd1 => utxd1,
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address => address,
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data => data,
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nSRAM_BE0 => nSRAM_BE0,
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nSRAM_BE1 => nSRAM_BE1,
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nSRAM_BE2 => nSRAM_BE2,
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nSRAM_BE3 => nSRAM_BE3,
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nSRAM_WE => nSRAM_WE,
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nSRAM_CE => nSRAM_CE,
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nSRAM_OE => nSRAM_OE,
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spw1_din => spw1_din,
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spw1_sin => spw1_sin,
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spw1_dout => spw1_dout,
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spw1_sout => spw1_sout,
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spw2_din => spw2_din,
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spw2_sin => spw2_sin,
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spw2_dout => spw2_dout,
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spw2_sout => spw2_sout,
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apbi_wfp => apbi_wfp,
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apbo_wfp => apbo_wfp,
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ahbi_wfp => ahbi_wfp,
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ahbo_wfp => ahbo_wfp,
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coarse_time => coarse_time,
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fine_time => fine_time);
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END beh;
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