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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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-------------------------------------------------------------------------------
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ENTITY TB_Data_Acquisition IS
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END TB_Data_Acquisition;
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-------------------------------------------------------------------------------
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ARCHITECTURE tb OF TB_Data_Acquisition IS
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COMPONENT TestModule_ADS7886
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GENERIC (
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freq : INTEGER;
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amplitude : INTEGER;
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impulsion : INTEGER);
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PORT (
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cnv_run : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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sck : IN STD_LOGIC;
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sdo : OUT STD_LOGIC);
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END COMPONENT;
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--COMPONENT Top_Data_Acquisition
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-- GENERIC (
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-- hindex : INTEGER;
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-- nb_burst_available_size : INTEGER := 11;
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-- nb_snapshot_param_size : INTEGER := 11;
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-- delta_snapshot_size : INTEGER := 16;
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-- delta_f2_f0_size : INTEGER := 10;
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-- delta_f2_f1_size : INTEGER := 10;
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-- tech : integer);
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-- PORT (
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-- cnv_run : IN STD_LOGIC;
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-- cnv : OUT STD_LOGIC;
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-- sck : OUT STD_LOGIC;
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-- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- cnv_clk : IN STD_LOGIC;
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-- cnv_rstn : IN STD_LOGIC;
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-- clk : IN STD_LOGIC;
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-- rstn : IN STD_LOGIC;
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-- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-- AHB_Master_In : IN AHB_Mst_In_Type;
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-- AHB_Master_Out : OUT AHB_Mst_Out_Type;
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-- coarse_time_0 : IN STD_LOGIC;
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-- data_shaping_SP0 : IN STD_LOGIC;
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-- data_shaping_SP1 : IN STD_LOGIC;
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-- data_shaping_R0 : IN STD_LOGIC;
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-- data_shaping_R1 : IN STD_LOGIC;
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-- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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-- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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-- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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-- enable_f0 : IN STD_LOGIC;
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-- enable_f1 : IN STD_LOGIC;
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-- enable_f2 : IN STD_LOGIC;
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-- enable_f3 : IN STD_LOGIC;
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-- burst_f0 : IN STD_LOGIC;
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-- burst_f1 : IN STD_LOGIC;
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-- burst_f2 : IN STD_LOGIC;
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-- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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-- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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-- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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-- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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--END COMPONENT;
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-- component ports
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SIGNAL cnv_rstn : STD_LOGIC;
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SIGNAL cnv : STD_LOGIC;
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SIGNAL rstn : STD_LOGIC;
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SIGNAL sck : STD_LOGIC;
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SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL run_cnv : STD_LOGIC;
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-- clock
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signal Clk : STD_LOGIC := '1';
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SIGNAL cnv_clk : STD_LOGIC := '1';
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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CONSTANT nb_burst_available_size : INTEGER := 12;
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CONSTANT nb_snapshot_param_size : INTEGER := 12;
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CONSTANT delta_snapshot_size : INTEGER := 16;
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CONSTANT delta_f2_f0_size : INTEGER := 20;
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CONSTANT delta_f2_f1_size : INTEGER := 16;
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SIGNAL AHB_Master_In : AHB_Mst_In_Type;
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SIGNAL AHB_Master_Out : AHB_Mst_Out_Type;
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SIGNAL coarse_time_0 : STD_LOGIC := '0';
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SIGNAL coarse_time_0_t : STD_LOGIC := '0';
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SIGNAL coarse_time_0_t2 : STD_LOGIC := '0';
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SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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SIGNAL enable_f0 : STD_LOGIC;
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SIGNAL enable_f1 : STD_LOGIC;
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SIGNAL enable_f2 : STD_LOGIC;
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SIGNAL enable_f3 : STD_LOGIC;
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SIGNAL burst_f0 : STD_LOGIC;
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SIGNAL burst_f1 : STD_LOGIC;
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SIGNAL burst_f2 : STD_LOGIC;
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SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_shaping_SP0 : STD_LOGIC;
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SIGNAL data_shaping_SP1 : STD_LOGIC;
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SIGNAL data_shaping_R0 : STD_LOGIC;
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SIGNAL data_shaping_R1 : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_type;
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-----------------------------------------------------------------------------
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN -- tb
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MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
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TestModule_ADS7886_u: TestModule_ADS7886
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GENERIC MAP (
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freq => 24*(I+1),
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amplitude => 30000/(I+1),
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impulsion => 0)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(I));
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END GENERATE MODULE_ADS7886;
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TestModule_ADS7886_u: TestModule_ADS7886
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GENERIC MAP (
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freq => 0,
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amplitude => 30000,
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impulsion => 1)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(7));
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-- clock generation
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Clk <= not Clk after 25 ns; -- 20 Mhz
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--cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
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cnv_clk <= not cnv_clk after 20346 ps; -- 49.152/2 MHz
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--type apb_slv_in_type is record
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-- psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
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-- penable : std_ulogic; -- strobe
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-- paddr : std_logic_vector(31 downto 0); -- address bus (byte)
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-- pwrite : std_ulogic; -- write
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-- pwdata : std_logic_vector(31 downto 0); -- write data bus
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-- pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
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-- testen : std_ulogic; -- scan test enable
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-- testrst : std_ulogic; -- scan test reset
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-- scanen : std_ulogic; -- scan enable
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-- testoen : std_ulogic; -- test output enable
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--end record;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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END IF;
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END PROCESS;
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait until Clk = '1';
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apbi <= apb_slv_in_none;
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rstn <= '0';
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cnv_rstn <= '0';
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run_cnv <= '0';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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rstn <= '1';
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cnv_rstn <= '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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run_cnv <= '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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apbi.psel(15) <= '1';
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apbi.penable <= '1';
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apbi.pwrite <= '1';
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-- 765432
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apbi.paddr(7 DOWNTO 2) <= "001000";
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apbi.pwdata(4 DOWNTO 0) <= "00000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001001";
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apbi.pwdata(6 DOWNTO 0) <= "0000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001010";
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apbi.pwdata <= "10000000000000000000000000000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001011";
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apbi.pwdata <= "10010000000000000000000000000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001100";
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apbi.pwdata <= "10100000000000000000000000000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001101";
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apbi.pwdata <= "10110000000000000000000000000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001110";
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apbi.pwdata(11 DOWNTO 0) <= "000000000000";
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wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "001111";
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|
apbi.pwdata(15 DOWNTO 0) <= "0000000000000001"; -- A => 1 * 100 ms
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|
wait until Clk = '1';
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|
apbi.paddr(7 DOWNTO 2) <= "010000"; -- delta_f2_f1
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|
apbi.pwdata(15 DOWNTO 0) <= "0000000001111000"; -- 0x78 = 120
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|
wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "010001"; -- delta_f2_f0
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|
apbi.pwdata(19 DOWNTO 0) <= "00000000001011111000"; -- 0x2f8 = 760
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|
wait until Clk = '1';
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apbi.paddr(7 DOWNTO 2) <= "010010"; -- nb_burst_available
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|
apbi.pwdata(11 DOWNTO 0) <= "000000001100"; -- 12 = 0xC
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|
wait until Clk = '1';
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|
apbi.paddr(7 DOWNTO 2) <= "010011"; -- nb_snapshot_param
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|
apbi.pwdata(11 DOWNTO 0) <= "000000001111"; -- 15 (+ 1)
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|
|
wait until Clk = '1';
|
|
|
wait until Clk = '1';
|
|
|
wait until Clk = '1';
|
|
|
wait until Clk = '1';
|
|
|
wait until Clk = '1';
|
|
|
apbi.paddr(7 DOWNTO 2) <= "001001";
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|
|
apbi.pwdata(6 DOWNTO 0) <= "0000111";
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|
|
wait until Clk = '1';
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|
|
apbi.psel(15) <= '1';
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|
apbi.penable <= '0';
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|
apbi.pwrite <= '0';
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|
|
wait until Clk = '1';
|
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|
|
|
|
wait;
|
|
|
|
|
|
end process WaveGen_Proc;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip
|
|
|
GENERIC MAP (
|
|
|
hindex => 2,
|
|
|
nb_burst_available_size => nb_burst_available_size,
|
|
|
nb_snapshot_param_size => nb_snapshot_param_size,
|
|
|
delta_snapshot_size => delta_snapshot_size,
|
|
|
delta_f2_f0_size => delta_f2_f0_size,
|
|
|
delta_f2_f1_size => delta_f2_f1_size,
|
|
|
tech => 0,
|
|
|
Mem_use => use_CEL
|
|
|
)
|
|
|
PORT MAP (
|
|
|
cnv_run => run_cnv,
|
|
|
cnv => cnv,
|
|
|
sck => sck,
|
|
|
sdo => sdo,
|
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|
cnv_clk => cnv_clk,
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|
cnv_rstn => cnv_rstn,
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|
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clk => clk,
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|
|
rstn => rstn,
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|
sample_f0_wen => sample_f0_wen,
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|
|
sample_f0_wdata => sample_f0_wdata,
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|
sample_f1_wen => sample_f1_wen,
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|
|
sample_f1_wdata => sample_f1_wdata,
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|
|
sample_f2_wen => sample_f2_wen,
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|
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sample_f2_wdata => sample_f2_wdata,
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|
|
sample_f3_wen => sample_f3_wen,
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|
|
sample_f3_wdata => sample_f3_wdata,
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|
AHB_Master_In => AHB_Master_In,
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|
|
AHB_Master_Out => AHB_Master_Out,
|
|
|
coarse_time_0 => coarse_time_0,
|
|
|
data_shaping_SP0 => data_shaping_SP0,
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|
|
data_shaping_SP1 => data_shaping_SP1,
|
|
|
data_shaping_R0 => data_shaping_R0,
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|
|
data_shaping_R1 => data_shaping_R1,
|
|
|
delta_snapshot => delta_snapshot,
|
|
|
delta_f2_f1 => delta_f2_f1,
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|
|
delta_f2_f0 => delta_f2_f0,
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|
|
enable_f0 => enable_f0,
|
|
|
enable_f1 => enable_f1,
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|
|
enable_f2 => enable_f2,
|
|
|
enable_f3 => enable_f3,
|
|
|
burst_f0 => burst_f0,
|
|
|
burst_f1 => burst_f1,
|
|
|
burst_f2 => burst_f2,
|
|
|
nb_burst_available => nb_burst_available,
|
|
|
nb_snapshot_param => nb_snapshot_param,
|
|
|
status_full => status_full,
|
|
|
status_full_ack => status_full_ack,
|
|
|
status_full_err => status_full_err,
|
|
|
status_new_err => status_new_err,
|
|
|
addr_data_f0 => addr_data_f0,
|
|
|
addr_data_f1 => addr_data_f1,
|
|
|
addr_data_f2 => addr_data_f2,
|
|
|
addr_data_f3 => addr_data_f3);
|
|
|
|
|
|
ready_matrix_f0_0 <= '0';
|
|
|
ready_matrix_f0_1 <= '0';
|
|
|
ready_matrix_f1 <= '0';
|
|
|
ready_matrix_f2 <= '0';
|
|
|
error_anticipating_empty_fifo <= '0';
|
|
|
error_bad_component_error <= '0';
|
|
|
debug_reg <= (OTHERS => '0');
|
|
|
|
|
|
|
|
|
lpp_top_apbreg_1: lpp_top_apbreg
|
|
|
GENERIC MAP (
|
|
|
nb_burst_available_size => nb_burst_available_size,
|
|
|
nb_snapshot_param_size => nb_snapshot_param_size,
|
|
|
delta_snapshot_size => delta_snapshot_size,
|
|
|
delta_f2_f0_size => delta_f2_f0_size,
|
|
|
delta_f2_f1_size => delta_f2_f1_size,
|
|
|
|
|
|
pindex => 15, -- todo
|
|
|
paddr => 15, -- todo
|
|
|
pmask => 16#fff#, -- todo
|
|
|
pirq => 15) -- todo
|
|
|
PORT MAP (
|
|
|
HCLK => clk,
|
|
|
HRESETn => rstn,
|
|
|
apbi => apbi, -- todo
|
|
|
apbo => apbo, -- todo
|
|
|
|
|
|
ready_matrix_f0_0 => ready_matrix_f0_0,
|
|
|
ready_matrix_f0_1 => ready_matrix_f0_1,
|
|
|
ready_matrix_f1 => ready_matrix_f1,
|
|
|
ready_matrix_f2 => ready_matrix_f2,
|
|
|
error_anticipating_empty_fifo => error_anticipating_empty_fifo,
|
|
|
error_bad_component_error => error_bad_component_error,
|
|
|
debug_reg => debug_reg,
|
|
|
status_ready_matrix_f0_0 => OPEN,
|
|
|
status_ready_matrix_f0_1 => OPEN,
|
|
|
status_ready_matrix_f1 => OPEN,
|
|
|
status_ready_matrix_f2 => OPEN,
|
|
|
status_error_anticipating_empty_fifo => OPEN,
|
|
|
status_error_bad_component_error => OPEN,
|
|
|
config_active_interruption_onNewMatrix => OPEN,
|
|
|
config_active_interruption_onError => OPEN,
|
|
|
addr_matrix_f0_0 => OPEN,
|
|
|
addr_matrix_f0_1 => OPEN,
|
|
|
addr_matrix_f1 => OPEN,
|
|
|
addr_matrix_f2 => OPEN,
|
|
|
|
|
|
status_full => status_full,
|
|
|
status_full_ack => status_full_ack,
|
|
|
status_full_err => status_full_err,
|
|
|
status_new_err => status_new_err,
|
|
|
|
|
|
data_shaping_BW => OPEN,
|
|
|
data_shaping_SP0 => data_shaping_SP0,
|
|
|
data_shaping_SP1 => data_shaping_SP1,
|
|
|
data_shaping_R0 => data_shaping_R0,
|
|
|
data_shaping_R1 => data_shaping_R1,
|
|
|
|
|
|
delta_snapshot => delta_snapshot,
|
|
|
delta_f2_f1 => delta_f2_f1,
|
|
|
delta_f2_f0 => delta_f2_f0,
|
|
|
nb_burst_available => nb_burst_available,
|
|
|
nb_snapshot_param => nb_snapshot_param,
|
|
|
enable_f0 => enable_f0,
|
|
|
enable_f1 => enable_f1,
|
|
|
enable_f2 => enable_f2,
|
|
|
enable_f3 => enable_f3,
|
|
|
burst_f0 => burst_f0,
|
|
|
burst_f1 => burst_f1,
|
|
|
burst_f2 => burst_f2,
|
|
|
addr_data_f0 => addr_data_f0,
|
|
|
addr_data_f1 => addr_data_f1,
|
|
|
addr_data_f2 => addr_data_f2,
|
|
|
addr_data_f3 => addr_data_f3);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
--PROCESS (clk, rstn)
|
|
|
--BEGIN -- PROCESS
|
|
|
-- IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
-- enable_f0 <= '0';
|
|
|
-- enable_f1 <= '0';
|
|
|
-- enable_f2 <= '0';
|
|
|
-- enable_f3 <= '0';
|
|
|
-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
|
|
|
-- enable_f0 <= '1'; --TODO test
|
|
|
-- enable_f1 <= '1';
|
|
|
-- enable_f2 <= '1';
|
|
|
-- enable_f3 <= '1';
|
|
|
-- END IF;
|
|
|
--END PROCESS;
|
|
|
|
|
|
--burst_f0 <= '0'; --TODO test
|
|
|
--burst_f1 <= '0'; --TODO test
|
|
|
--burst_f2 <= '0';
|
|
|
|
|
|
--data_shaping_SP0 <= '0';
|
|
|
--data_shaping_SP1 <= '0';
|
|
|
--data_shaping_R0 <= '1';
|
|
|
--data_shaping_R1 <= '1';
|
|
|
|
|
|
--delta_snapshot <= "0000000000000001";
|
|
|
--nb_snapshot_param <= "00000001110"; -- 14+1 = 15
|
|
|
--delta_f2_f0 <= "10 1001 1001";--665 = 14/2*96 -14/2
|
|
|
--delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4
|
|
|
|
|
|
-- A redefinir car ca ne tombe pas correctement ... ???
|
|
|
--nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34
|
|
|
--nb_snapshot_param <= "00000001111"; -- x+1 = 16
|
|
|
--delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2
|
|
|
--delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4
|
|
|
|
|
|
--addr_data_f0 <= "00000000000000000000000000000000";
|
|
|
--addr_data_f1 <= "00010000000000000000000000000000";
|
|
|
--addr_data_f2 <= "00100000000000000000000000000000";
|
|
|
--addr_data_f3 <= "00110000000000000000000000000000";
|
|
|
|
|
|
--PROCESS (clk, rstn)
|
|
|
--BEGIN -- PROCESS
|
|
|
-- IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
-- status_full_ack <= (OTHERS => '0');
|
|
|
-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
|
|
|
-- status_full_ack <= status_full;
|
|
|
-- END IF;
|
|
|
--END PROCESS;
|
|
|
|
|
|
|
|
|
coarse_time_0 <= not coarse_time_0 AFTER 100 ms;
|
|
|
|
|
|
--PROCESS (clk, rstn)
|
|
|
--BEGIN -- PROCESS
|
|
|
-- IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
-- coarse_time_0_t2 <= '0';
|
|
|
-- coarse_time_0 <= '0';
|
|
|
-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
|
|
|
-- coarse_time_0_t2 <= coarse_time_0_t;
|
|
|
-- coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2);
|
|
|
-- END IF;
|
|
|
--END PROCESS;
|
|
|
|
|
|
|
|
|
AHB_Master_In.HGRANT(2) <= '1';
|
|
|
AHB_Master_In.HREADY <= '1';
|
|
|
AHB_Master_In.HRESP <= HRESP_OKAY;
|
|
|
|
|
|
|
|
|
END tb;
|
|
|
|
