HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ICI4-Integ1/config.vhd

Fixed bug, now minor and major frame pulses have the good width....

Fixed bug, now minor and major frame pulses have the good width. (one sck period and not one word clock period)

jeandet - - Load All Authors

File last commit:

r168:0b190be76d60 alexis


                r222:b37e19fe4c0b

alexis

Download file

             config.vhd
        
                    52 lines
            
             | 2.0 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / designs / ICI4-Integ1 / config.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      -----------------------------------------------------------------------------

      -- LEON3 Demonstration design test bench configuration

      -- Copyright (C) 2009 Aeroflex Gaisler

      ------------------------------------------------------------------------------

      library techmap;

      use techmap.gencomp.all;

      library ieee;

      use ieee.std_logic_1164.all;

      package config is

      -- Technology and synthesis options

        constant CFG_FABTECH : integer := spartan6;

        constant CFG_MEMTECH : integer := spartan6;

        constant CFG_PADTECH : integer := spartan6;

      -- Clock generator

        constant CFG_CLKTECH : integer := spartan6;

        constant SEND_CONSTANT_DATA : integer := 1;

        constant SEND_MINF_VALUE    : integer := 1;

      constant LF1cst :   std_logic_vector(15 downto 0) := X"1111";

      constant LF2cst :   std_logic_vector(15 downto 0) := X"2222";

      constant LF3cst :   std_logic_vector(15 downto 0) := X"3333";

      constant  AMR1Xcst   :     std_logic_vector(23 downto 0):= X"444444";

      constant  AMR1Ycst   :     std_logic_vector(23 downto 0):= X"555555";

      constant  AMR1Zcst   :     std_logic_vector(23 downto 0):= X"666666";

      constant  AMR2Xcst   :     std_logic_vector(23 downto 0):= X"777777";

      constant  AMR2Ycst   :     std_logic_vector(23 downto 0):= X"888888";

      constant  AMR2Zcst   :     std_logic_vector(23 downto 0):= X"999999";

      constant  AMR3Xcst   :     std_logic_vector(23 downto 0):= X"AAAAAA";

      constant  AMR3Ycst   :     std_logic_vector(23 downto 0):= X"BBBBBB";

      constant  AMR3Zcst   :     std_logic_vector(23 downto 0):= X"CCCCCC";

      constant  AMR4Xcst   :     std_logic_vector(23 downto 0):= X"DDDDDD";

      constant  AMR4Ycst   :     std_logic_vector(23 downto 0):= X"EEEEEE";

      constant  AMR4Zcst   :     std_logic_vector(23 downto 0):= X"FFFFFF";

      constant  Temp1cst   :     std_logic_vector(23 downto 0):= X"121212";

      constant  Temp2cst   :     std_logic_vector(23 downto 0):= X"343434";

      constant  Temp3cst   :     std_logic_vector(23 downto 0):= X"565656";

      constant  Temp4cst   :     std_logic_vector(23 downto 0):= X"787878";

      end;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages




				-----------------------------------------------------------------------------
				-- LEON3 Demonstration design test bench configuration
				-- Copyright (C) 2009 Aeroflex Gaisler
				------------------------------------------------------------------------------


				library techmap;
				use techmap.gencomp.all;
				library ieee;
				use ieee.std_logic_1164.all;

				package config is
				-- Technology and synthesis options
				constant CFG_FABTECH : integer := spartan6;
				constant CFG_MEMTECH : integer := spartan6;
				constant CFG_PADTECH : integer := spartan6;
				-- Clock generator
				constant CFG_CLKTECH : integer := spartan6;
				constant SEND_CONSTANT_DATA : integer := 1;
				constant SEND_MINF_VALUE : integer := 1;



				constant LF1cst : std_logic_vector(15 downto 0) := X"1111";
				constant LF2cst : std_logic_vector(15 downto 0) := X"2222";
				constant LF3cst : std_logic_vector(15 downto 0) := X"3333";


				constant AMR1Xcst : std_logic_vector(23 downto 0):= X"444444";
				constant AMR1Ycst : std_logic_vector(23 downto 0):= X"555555";
				constant AMR1Zcst : std_logic_vector(23 downto 0):= X"666666";

				constant AMR2Xcst : std_logic_vector(23 downto 0):= X"777777";
				constant AMR2Ycst : std_logic_vector(23 downto 0):= X"888888";
				constant AMR2Zcst : std_logic_vector(23 downto 0):= X"999999";

				constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA";
				constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB";
				constant AMR3Zcst : std_logic_vector(23 downto 0):= X"CCCCCC";

				constant AMR4Xcst : std_logic_vector(23 downto 0):= X"DDDDDD";
				constant AMR4Ycst : std_logic_vector(23 downto 0):= X"EEEEEE";
				constant AMR4Zcst : std_logic_vector(23 downto 0):= X"FFFFFF";

				constant Temp1cst : std_logic_vector(23 downto 0):= X"121212";
				constant Temp2cst : std_logic_vector(23 downto 0):= X"343434";
				constant Temp3cst : std_logic_vector(23 downto 0):= X"565656";
				constant Temp4cst : std_logic_vector(23 downto 0):= X"787878";
				end;