##// END OF EJS Templates
Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r548:8b4d3dd621c2 JC
r674:b0efa9138022 default
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vhdlsyn.txt
2 lines | 33 B | text/plain | TextLexer
lpp_Header.vhd
HeaderBuilder.vhd