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correction - decalage 1 data MS
pellion -
r548:8b4d3dd621c2 JC
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@@ -0,0 +1,2
1 lpp_Header.vhd
2 HeaderBuilder.vhd
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@@ -43,7 +43,8 FILESKIP =i2cmst.vhd \
43 Top_MatrixSpec.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd \
44 APB_FFT.vhd \
45 CoreFFT_simu.vhd \
45 CoreFFT_simu.vhd \
46 lpp_lfr_apbreg_simu.vhd
46 lpp_lfr_apbreg_simu.vhd \
47 MUXN.vhd
47
48
48 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/software/leon3/Makefile
50 include $(GRLIB)/software/leon3/Makefile
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@@ -43,6 +43,7 ARCHITECTURE beh OF data_write_with_burs
43 SIGNAL data_ren_s : STD_LOGIC;
43 SIGNAL data_ren_s : STD_LOGIC;
44 SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
44 SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
45 SIGNAL data_in_val : STD_LOGIC;
45 SIGNAL data_in_val : STD_LOGIC;
46
46
47
47 BEGIN
48 BEGIN
48
49
@@ -52,6 +53,7 BEGIN
52 ren_counter <= 0;
53 ren_counter <= 0;
53 data_ren_s <= '1';
54 data_ren_s <= '1';
54 data_s <= (OTHERS => '0');
55 data_s <= (OTHERS => '0');
56 data_in_val <= '0';
55 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
57 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
56 data_s <= data;
58 data_s <= data;
57 data_ren_s <= '1';
59 data_ren_s <= '1';
@@ -61,11 +63,11 BEGIN
61 IF ren_counter > 0 THEN
63 IF ren_counter > 0 THEN
62 ren_counter <= ren_counter - 1;
64 ren_counter <= ren_counter - 1;
63 data_ren_s <= '0';
65 data_ren_s <= '0';
64 END IF;
66 END IF;
67 data_in_val <= NOT data_ren_s;
65 END IF;
68 END IF;
66 END PROCESS;
69 END PROCESS;
67
70
68 data_in_val <= NOT data_ren_s;
69 data_ren <= data_ren_s;
71 data_ren <= data_ren_s;
70
72
71 data_write_1: data_write
73 data_write_1: data_write
@@ -75,7 +77,7 BEGIN
75 PORT MAP (
77 PORT MAP (
76 clk => clk,
78 clk => clk,
77 data_in_val => data_in_val,
79 data_in_val => data_in_val,
78 data => data_s,
80 data => data,
79 close_file => close_file);
81 close_file => close_file);
80
82
81 END beh;
83 END beh;
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@@ -52,5 +52,6 vsim work.testbench \
52 -goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
52 -goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
53 -goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
53 -goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
54 when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
54 when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
55
55 run -all
56 run -all
56 exit
57 exit
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@@ -103,6 +103,9 ARCHITECTURE behav OF testbench IS
103 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
103 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
104 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
106 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
107 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
108 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
106 SIGNAL time_counter : INTEGER;
109 SIGNAL time_counter : INTEGER;
107
110
108 SIGNAL new_fine_time : STD_LOGIC := '0';
111 SIGNAL new_fine_time : STD_LOGIC := '0';
@@ -367,6 +370,10 BEGIN
367 sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
370 sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
368 sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
371 sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
369
372
373 sample_f0_time <= coarse_time & fine_time;
374 sample_f1_time <= coarse_time & fine_time;
375 sample_f2_time <= coarse_time & fine_time;
376
370 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
371 -- DUT
378 -- DUT
372 -----------------------------------------------------------------------------
379 -----------------------------------------------------------------------------
@@ -383,17 +390,20 BEGIN
383 -----------------------------------------------------------------------------
390 -----------------------------------------------------------------------------
384 start_date => start_date,
391 start_date => start_date,
385 coarse_time => coarse_time,
392 coarse_time => coarse_time,
386 fine_time => fine_time,
393 -- fine_time => fine_time,
387
394
388 -------------------------------------------------------------------------
395 -------------------------------------------------------------------------
389 -- DATA IN
396 -- DATA IN
390 -------------------------------------------------------------------------
397 -------------------------------------------------------------------------
391 sample_f0_wen => sample_f0_wen_v, --
398 sample_f0_wen => sample_f0_wen_v, --
392 sample_f0_wdata => sample_f0_wdata,
399 sample_f0_wdata => sample_f0_wdata,
400 sample_f0_time => sample_f0_time,
393 sample_f1_wen => sample_f1_wen_v,
401 sample_f1_wen => sample_f1_wen_v,
394 sample_f1_wdata => sample_f1_wdata,
402 sample_f1_wdata => sample_f1_wdata,
403 sample_f1_time => sample_f1_time,
395 sample_f2_wen => sample_f2_wen_v,
404 sample_f2_wen => sample_f2_wen_v,
396 sample_f2_wdata => sample_f2_wdata,
405 sample_f2_wdata => sample_f2_wdata,
406 sample_f2_time => sample_f2_time,
397
407
398 -------------------------------------------------------------------------
408 -------------------------------------------------------------------------
399 -- DMA OUT
409 -- DMA OUT
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@@ -1,7 +1,22
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
2 quietly WaveActivateNextPane {} 0
12 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
4 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
5 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
6 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
7 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
@@ -19,11 +34,156 add wave -noupdate -expand -group DMA_in
19 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
20 add wave -noupdate /testbench/dma_ren_counter
35 add wave -noupdate /testbench/dma_ren_counter
21 add wave -noupdate /testbench/dma_output_counter
36 add wave -noupdate /testbench/dma_output_counter
37 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) -radix hexadecimal} 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/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
22 TreeUpdate [SetDefaultTree]
182 TreeUpdate [SetDefaultTree]
23 WaveRestoreCursors {{Cursor 1} {10933060000 ps} 0}
183 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
24 quietly wave cursor active 1
184 quietly wave cursor active 6
25 configure wave -namecolwidth 339
185 configure wave -namecolwidth 573
26 configure wave -valuecolwidth 100
186 configure wave -valuecolwidth 108
27 configure wave -justifyvalue left
187 configure wave -justifyvalue left
28 configure wave -signalnamewidth 0
188 configure wave -signalnamewidth 0
29 configure wave -snapdistance 10
189 configure wave -snapdistance 10
@@ -36,4 +196,4 configure wave -griddelta 40
36 configure wave -timeline 0
196 configure wave -timeline 0
37 configure wave -timelineunits ns
197 configure wave -timelineunits ns
38 update
198 update
39 WaveRestoreZoom {0 ps} {42718685333 ps}
199 WaveRestoreZoom {0 ps} {14085099 ns}
Show file before | Show file after | Hide comments
@@ -62,19 +62,24 ARCHITECTURE beh OF MS_calculation IS
62 --SIGNAL res_wen_reg3 : STD_LOGIC;
62 --SIGNAL res_wen_reg3 : STD_LOGIC;
63
63
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65
66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
65
69
66 BEGIN
70 BEGIN
67
71
68
72
69 PROCESS (clk, rstn)
73 --PROCESS (clk, rstn)
70 BEGIN -- PROCESS
74 --BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
75 -- IF rstn = '0' THEN -- asynchronous reset (active low)
72 fifo_in_ren <= "11";
76 -- fifo_in_ren <= "11";
73 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
77 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
74 fifo_in_ren <= fifo_in_ren_s;
78 -- fifo_in_ren <= fifo_in_ren_s;
75 END IF;
79 -- END IF;
76 END PROCESS;
80 --END PROCESS;
77
81
82 fifo_in_ren <= fifo_in_ren_s;
78
83
79 PROCESS (clk, rstn)
84 PROCESS (clk, rstn)
80 BEGIN
85 BEGIN
@@ -89,6 +94,7 BEGIN
89 select_op1 <= select_R0(0);
94 select_op1 <= select_R0(0);
90 select_op2 <= select_R0;
95 select_op2 <= select_R0;
91 res_wen <= '1';
96 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
92
98
93 ELSIF clk'EVENT AND clk = '1' THEN
99 ELSIF clk'EVENT AND clk = '1' THEN
94 select_ctrl <= select_ctrl_NOP;
100 select_ctrl <= select_ctrl_NOP;
@@ -97,6 +103,7 BEGIN
97 fifo_in_ren_s <= "11";
103 fifo_in_ren_s <= "11";
98 res_wen <= '1';
104 res_wen <= '1';
99 correlation_done <= '0';
105 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
100 CASE state IS
107 CASE state IS
101 WHEN IDLE =>
108 WHEN IDLE =>
102 IF correlation_start = '1' THEN
109 IF correlation_start = '1' THEN
@@ -106,7 +113,7 BEGIN
106 ELSE
113 ELSE
107 correlation_begin <= '1';
114 correlation_begin <= '1';
108 state <= S1a;
115 state <= S1a;
109 fifo_in_ren_s <= "10";
116 --fifo_in_ren_s <= "10";
110 END IF;
117 END IF;
111 ELSE
118 ELSE
112 IF fifo_out_full = '1' THEN
119 IF fifo_out_full = '1' THEN
@@ -114,7 +121,7 BEGIN
114 ELSE
121 ELSE
115 correlation_begin <= '1';
122 correlation_begin <= '1';
116 state <= S1;
123 state <= S1;
117 fifo_in_ren_s <= "00";
124 --fifo_in_ren_s <= "00";
118 END IF;
125 END IF;
119 END IF;
126 END IF;
120 END IF;
127 END IF;
@@ -126,7 +133,7 BEGIN
126 IF fifo_out_full = '0' THEN
133 IF fifo_out_full = '0' THEN
127 correlation_begin <= '1';
134 correlation_begin <= '1';
128 state <= S1;
135 state <= S1;
129 fifo_in_ren_s <= "00";
136 --fifo_in_ren_s <= "00";
130 END IF;
137 END IF;
131 WHEN S1 =>
138 WHEN S1 =>
132 select_ctrl <= select_ctrl_MULT;
139 select_ctrl <= select_ctrl_MULT;
@@ -144,8 +151,9 BEGIN
144 WHEN S3 =>
151 WHEN S3 =>
145 select_ctrl <= select_ctrl_MULT;
152 select_ctrl <= select_ctrl_MULT;
146 --ALU_CTRL <= ALU_CTRL_MULT;
153 --ALU_CTRL <= ALU_CTRL_MULT;
147 select_op1 <= select_I0(0);
154 select_op1 <= select_I0(0);
148 select_op2 <= select_R1;
155 select_op2 <= select_R1;
156 fifo_in_ren_s <= fifo_in_empty;
149 state <= S4;
157 state <= S4;
150 WHEN S4 =>
158 WHEN S4 =>
151 select_ctrl <= select_ctrl_MACn;
159 select_ctrl <= select_ctrl_MACn;
@@ -155,7 +163,7 BEGIN
155 res_wen <= '0';
163 res_wen <= '0';
156 IF fifo_in_empty = "00" THEN
164 IF fifo_in_empty = "00" THEN
157 state <= S1;
165 state <= S1;
158 fifo_in_ren_s <= "00";
166 -- fifo_in_ren_s <= "00";
159 ELSE
167 ELSE
160 correlation_done <= '1';
168 correlation_done <= '1';
161 state <= IDLE;
169 state <= IDLE;
@@ -170,13 +178,14 BEGIN
170 IF fifo_out_full = '0' THEN
178 IF fifo_out_full = '0' THEN
171 correlation_begin <= '1';
179 correlation_begin <= '1';
172 state <= S1a;
180 state <= S1a;
173 fifo_in_ren_s <= "10";
181 --fifo_in_ren_s <= "10";
174 END IF;
182 END IF;
175 WHEN S1a =>
183 WHEN S1a =>
176 select_ctrl <= select_ctrl_MULT;
184 select_ctrl <= select_ctrl_MULT;
177 --ALU_CTRL <= ALU_CTRL_MULT;
185 --ALU_CTRL <= ALU_CTRL_MULT;
178 select_op1 <= select_R0(0);
186 select_op1 <= select_R0(0);
179 select_op2 <= select_R0;
187 select_op2 <= select_R0;
188 fifo_in_ren_s(0) <= fifo_in_empty(0);
180 state <= S2a;
189 state <= S2a;
181 WHEN S2a =>
190 WHEN S2a =>
182 select_ctrl <= select_ctrl_MAC;
191 select_ctrl <= select_ctrl_MAC;
@@ -186,7 +195,7 BEGIN
186 res_wen <= '0';
195 res_wen <= '0';
187 IF fifo_in_empty(0) = '0' THEN
196 IF fifo_in_empty(0) = '0' THEN
188 state <= S1a;
197 state <= S1a;
189 fifo_in_ren_s <= "10";
198 --fifo_in_ren_s <= "10";
190 ELSE
199 ELSE
191 correlation_done <= '1';
200 correlation_done <= '1';
192 state <= IDLE;
201 state <= IDLE;
Show file before | Show file after | Hide comments
@@ -41,7 +41,7 ENTITY lpp_lfr_ms IS
41 --
41 --
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45
45
46 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
47 -- DMA
47 -- DMA
@@ -201,6 +201,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
201 SIGNAL fifo_0_ready : STD_LOGIC;
201 SIGNAL fifo_0_ready : STD_LOGIC;
202 SIGNAL fifo_1_ready : STD_LOGIC;
202 SIGNAL fifo_1_ready : STD_LOGIC;
203 SIGNAL fifo_ongoing : STD_LOGIC;
203 SIGNAL fifo_ongoing : STD_LOGIC;
204 SIGNAL fifo_ongoing_reg : STD_LOGIC;
204
205
205 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
206 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
206 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
207 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
@@ -998,7 +999,9 BEGIN
998 fifo_0_ready <= '0';
999 fifo_0_ready <= '0';
999 fifo_1_ready <= '0';
1000 fifo_1_ready <= '0';
1000 fifo_ongoing <= '0';
1001 fifo_ongoing <= '0';
1002 fifo_ongoing_reg <= '0';
1001 ELSIF clk'EVENT AND clk = '1' THEN
1003 ELSIF clk'EVENT AND clk = '1' THEN
1004 fifo_ongoing_reg <= fifo_ongoing;
1002 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1005 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1003 fifo_ongoing <= '1';
1006 fifo_ongoing <= '1';
1004 fifo_0_ready <= '0';
1007 fifo_0_ready <= '0';
@@ -1031,7 +1034,7 BEGIN
1031 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1034 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1032 status_component_fifo_1;
1035 status_component_fifo_1;
1033
1036
1034 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1037 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1035 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1038 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1036
1039
1037
1040
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