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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)
pellion - - Load All Authors

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r440:c7a9f0e6d39e JC
r674:b0efa9138022 default
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run.do
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/ designs / Validation_LFR / run.do
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log -R *
do wave.do
run -all