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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:26:29 12/07/2013
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-- Design Name:
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-- Module Name: DAC8581 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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library LPP;
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use lpp.lpp_cna.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DAC8581 is
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generic(
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clkfreq : integer := 100;
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ChanCount : integer := 8
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);
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Port ( clk : in STD_LOGIC;
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rstn : in STD_LOGIC;
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smpclk : in STD_LOGIC;
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sclk : out STD_LOGIC;
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csn : out STD_LOGIC;
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sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
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smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
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);
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end DAC8581;
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architecture Behavioral of DAC8581 is
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signal smpclk_reg : std_logic;
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signal sclk_gen : std_logic_vector(3 downto 0);
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signal sclk_net : std_logic;
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signal load : std_logic;
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signal load_reg : std_logic;
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signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
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signal csn_sreg : std_logic;
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signal shift_counter : integer range 0 to 16;
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signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0);
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begin
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sclk_net <= sclk_gen(2);
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sclk <= sclk_net;
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process(rstn,clk)
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begin
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if rstn ='0' then
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smpclk_reg <= '0';
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sclk_gen <= "0000";
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load <= '0';
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elsif clk'event and clk = '1' then
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smpclk_reg <= smpclk;
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sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
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if smpclk_reg = '0' and smpclk = '1' then
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load <= '1';
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else
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load <= '0';
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end if;
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end if;
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end process;
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process(load,sclk_net)
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begin
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if load ='1' then
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load_reg <= '1';
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elsif sclk_net'event and sclk_net = '1' then
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load_reg <= '0';
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end if;
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end process;
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process(rstn,sclk_net)
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begin
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if rstn ='0' then
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data_sreg <= smp_in;
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csn_sreg <= '1';
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elsif sclk_net'event and sclk_net = '1' then
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if load_reg = '1' then
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data_sreg <= smp_in;
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shift_counter <= 0;
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csn_sreg <= '1';
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else
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all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
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all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
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data_sreg(I,J+1) <= data_sreg(I,J);
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END LOOP all_bits0;
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data_sreg(I,0) <= '1';
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END LOOP all_chanel0;
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if shift_counter /= 16 then
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shift_counter <= shift_counter + 1;
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csn_sreg <= '0';
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else
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csn_sreg <= '1';
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end if;
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end if;
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end if;
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end process;
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process(rstn,sclk_net)
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begin
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if rstn ='0' then
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all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
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sdo_int(I) <= '1';
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sdo(I) <= '1';
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END LOOP all_chanel2;
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csn <= '1';
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elsif sclk_net'event and sclk_net = '0' then
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all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
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sdo_int(I) <= data_sreg(I,15);
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END LOOP all_chanel1;
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sdo <= sdo_int;
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csn <= csn_sreg;
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end if;
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end process;
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end Behavioral;
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