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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:26:29 12/07/2013 
-- Design Name: 
-- Module Name:    DAC8581 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library LPP;
use lpp.lpp_cna.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC8581 is
   generic(
		clkfreq   : integer := 100;
		ChanCount : integer := 8
		);
    Port ( clk : in  STD_LOGIC;
           rstn : in  STD_LOGIC;
           smpclk : in  STD_LOGIC;
           sclk : out  STD_LOGIC;
           csn : out  STD_LOGIC;
           sdo : out  STD_LOGIC_VECTOR (ChanCount-1 downto 0);
           smp_in : in  CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
	);
end DAC8581;

architecture Behavioral of DAC8581 is

signal smpclk_reg   : std_logic;
signal sclk_gen     : std_logic_vector(3 downto 0);
signal sclk_net     : std_logic;
signal load         : std_logic;
signal load_reg     : std_logic;
signal data_sreg	  : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);

signal csn_sreg     : std_logic;
signal shift_counter : integer range 0 to 16;
signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0);
begin

	 
	 
sclk_net  <= sclk_gen(2);
sclk		 <= sclk_net;

process(rstn,clk)
begin
if rstn ='0' then
	smpclk_reg	<= '0';
	sclk_gen		<= "0000";
	load        <= '0';
elsif clk'event and clk = '1' then 
	smpclk_reg	<= smpclk;
	sclk_gen  <= std_logic_vector(unsigned(sclk_gen) + 1);
	if smpclk_reg = '0' and smpclk = '1' then
		load <= '1';
	else
		load <= '0';
	end if;
	
end if;
end process;

process(load,sclk_net)
begin
if load ='1' then
	load_reg     <= '1';
elsif sclk_net'event and sclk_net = '1' then
   load_reg     <= '0';
end if;
end process;

process(rstn,sclk_net)
begin
if rstn ='0' then
	data_sreg     <= smp_in;
   csn_sreg      <= '1';
elsif sclk_net'event and sclk_net = '1' then
   if load_reg = '1' then
		data_sreg     <= smp_in;
      shift_counter <= 0;
		csn_sreg      <= '1';
   else
		all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
			all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
				data_sreg(I,J+1)   <= data_sreg(I,J);
			END LOOP all_bits0;
				data_sreg(I,0)   <= '1';
		END LOOP all_chanel0;
		if shift_counter /= 16 then
			shift_counter    <= shift_counter + 1;
			csn_sreg         <= '0';
		else 
			csn_sreg	        <= '1';
		end if;
		
   end if;
end if;
end process;

process(rstn,sclk_net)
begin
if rstn ='0' then
	all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
      sdo_int(I) <= '1';
		sdo(I) <= '1';
   END LOOP all_chanel2;
   csn     <= '1';
elsif sclk_net'event and sclk_net = '0' then 
   all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
      sdo_int(I) <= data_sreg(I,15);
   END LOOP all_chanel1;
	sdo <= sdo_int;
	csn <= csn_sreg;
end if;
end process;



end Behavioral;