HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_memory/vhdlsyn.txt

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

pellion - - Load All Authors

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r416:92057c9e9a3b JC


                r594:a9702b7364d2

simu_with_Leon3

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				lpp_memory.vhd
				lpp_FIFO.vhd
				lpp_FIFO_4_Shared.vhd
				lpp_FIFO_control.vhd
				lpp_FIFO_4_Shared_headreg_latency_0.vhd
				lpp_FIFO_4_Shared_headreg_latency_1.vhd
				lppFIFOxN.vhd

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