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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY IIR_CEL_CTRLR_v2 IS
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GENERIC (
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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Sample_SZ : INTEGER := 18;
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Coef_SZ : INTEGER := 9;
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Coef_Nb : INTEGER := 25;
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Coef_sel_SZ : INTEGER := 5;
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Cels_count : INTEGER := 5;
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ChanelsCount : INTEGER := 8;
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FILENAME : STRING := "");
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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virg_pos : IN INTEGER;
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coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
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END IIR_CEL_CTRLR_v2;
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ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
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COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
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GENERIC (
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tech : INTEGER;
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Mem_use : INTEGER;
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Sample_SZ : INTEGER;
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Coef_SZ : INTEGER;
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Coef_Nb : INTEGER;
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Coef_sel_SZ : INTEGER;
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FILENAME : STRING);
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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virg_pos : IN INTEGER;
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coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
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in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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init_mem_done : out STD_LOGIC;
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ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_write : IN STD_LOGIC;
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ram_read : IN STD_LOGIC;
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raddr_rst : IN STD_LOGIC;
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raddr_add1 : IN STD_LOGIC;
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waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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alu_sel_input : IN STD_LOGIC;
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alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
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alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT IIR_CEL_CTRLR_v2_CONTROL
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GENERIC (
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Coef_sel_SZ : INTEGER;
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Cels_count : INTEGER;
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ChanelsCount : INTEGER);
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in_rot : OUT STD_LOGIC;
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sample_out_val : OUT STD_LOGIC;
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sample_out_rot : OUT STD_LOGIC;
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init_mem_done : in STD_LOGIC; --TODO
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in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_write : OUT STD_LOGIC;
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ram_read : OUT STD_LOGIC;
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raddr_rst : OUT STD_LOGIC;
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raddr_add1 : OUT STD_LOGIC;
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waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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alu_sel_input : OUT STD_LOGIC;
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alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
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alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
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END COMPONENT;
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SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL ram_write : STD_LOGIC;
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SIGNAL ram_read : STD_LOGIC;
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SIGNAL raddr_rst : STD_LOGIC;
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SIGNAL raddr_add1 : STD_LOGIC;
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SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL alu_sel_input : STD_LOGIC;
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SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
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SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
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SIGNAL sample_in_rotate : STD_LOGIC;
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SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL sample_out_val_s : STD_LOGIC;
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SIGNAL sample_out_val_s2 : STD_LOGIC;
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SIGNAL sample_out_rot_s : STD_LOGIC;
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SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
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SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
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signal init_mem_done : std_logic;
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BEGIN
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IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
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GENERIC MAP (
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tech => tech,
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Mem_use => Mem_use,
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Sample_SZ => Sample_SZ,
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Coef_SZ => Coef_SZ,
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Coef_Nb => Coef_Nb,
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Coef_sel_SZ => Coef_sel_SZ,
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FILENAME => FILENAME)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => virg_pos,
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coefs => coefs,
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--CTRL
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in_sel_src => in_sel_src,
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init_mem_done => init_mem_done, --TODO
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ram_sel_Wdata => ram_sel_Wdata,
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ram_write => ram_write,
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ram_read => ram_read,
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raddr_rst => raddr_rst,
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raddr_add1 => raddr_add1,
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waddr_previous => waddr_previous,
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alu_sel_input => alu_sel_input,
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alu_sel_coeff => alu_sel_coeff,
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alu_ctrl => alu_ctrl,
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alu_comp => "00",
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--DATA
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sample_in => sample_in_s,
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sample_out => sample_out_s);
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IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
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GENERIC MAP (
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Coef_sel_SZ => Coef_sel_SZ,
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Cels_count => Cels_count,
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ChanelsCount => ChanelsCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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sample_in_val => sample_in_val,
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sample_in_rot => sample_in_rotate,
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sample_out_val => sample_out_val_s,
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sample_out_rot => sample_out_rot_s,
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init_mem_done => init_mem_done, --TODO
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in_sel_src => in_sel_src,
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ram_sel_Wdata => ram_sel_Wdata,
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ram_write => ram_write,
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ram_read => ram_read,
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raddr_rst => raddr_rst,
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raddr_add1 => raddr_add1,
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waddr_previous => waddr_previous,
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alu_sel_input => alu_sel_input,
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alu_sel_coeff => alu_sel_coeff,
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alu_ctrl => alu_ctrl);
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-----------------------------------------------------------------------------
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-- SAMPLE IN
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-----------------------------------------------------------------------------
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loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
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loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_in_buf(I, J) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF sample_in_val = '1' THEN
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sample_in_buf(I, J) <= sample_in(I, J);
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ELSIF sample_in_rotate = '1' THEN
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sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
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END IF;
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END IF;
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END PROCESS;
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END GENERATE loop_all_chanel;
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sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
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END GENERATE loop_all_sample;
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-----------------------------------------------------------------------------
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-- SAMPLE OUT
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_out_val <= '0';
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sample_out_val_s2 <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_out_val <= sample_out_val_s2;
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sample_out_val_s2 <= sample_out_val_s;
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END IF;
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END PROCESS;
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chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_out_s2(ChanelsCount-1, I) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF sample_out_rot_s = '1' THEN
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sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
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END IF;
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END IF;
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END PROCESS;
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END GENERATE chanel_HIGH;
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chanel_more : IF ChanelsCount > 1 GENERATE
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all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
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all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_out_s2(J-1, I) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF sample_out_rot_s = '1' THEN
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sample_out_s2(J-1, I) <= sample_out_s2(J, I);
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_bit;
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END GENERATE all_chanel;
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END GENERATE chanel_more;
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sample_out <= sample_out_s2;
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END ar_IIR_CEL_CTRLR_v2;
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