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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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PACKAGE lpp_ad_conv IS
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--CONSTANT AD7688 : INTEGER := 0;
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--CONSTANT ADS7886 : INTEGER := 1;
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TYPE AD7688_out IS
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RECORD
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CNV : STD_LOGIC;
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SCK : STD_LOGIC;
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END RECORD;
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TYPE AD7688_in_element IS
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RECORD
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SDI : STD_LOGIC;
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END RECORD;
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TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
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TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
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SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
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SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
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SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
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SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
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SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
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TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
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TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
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TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
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TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
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TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
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TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
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COMPONENT RHF1401_drvr IS
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GENERIC(
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ChanelCount : INTEGER := 8);
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PORT (
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cnv_clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ADC_data : IN Samples14;
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--ADC_smpclk : OUT STD_LOGIC;
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ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT top_ad_conv_RHF1401
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GENERIC (
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ChanelCount : INTEGER;
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ncycle_cnv_high : INTEGER := 79;
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ncycle_cnv : INTEGER := 500);
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PORT (
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ADC_data : IN Samples14;
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ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT TestModule_RHF1401
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GENERIC (
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freq : INTEGER;
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amplitude : INTEGER;
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impulsion : INTEGER);
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PORT (
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ADC_smpclk : IN STD_LOGIC;
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ADC_OEB_bar : IN STD_LOGIC;
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ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
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END COMPONENT;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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COMPONENT ADS7886_drvr
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GENERIC (
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ChanelCount : INTEGER;
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ncycle_cnv_high : INTEGER := 79;
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ncycle_cnv : INTEGER := 500);
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PORT (
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT AD7688_drvr IS
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GENERIC(ChanelCount : INTEGER;
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clkkHz : INTEGER);
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PORT (clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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smplClk : IN STD_LOGIC;
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DataReady : OUT STD_LOGIC;
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smpout : OUT Samples(ChanelCount-1 DOWNTO 0);
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AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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AD_out : OUT AD7688_out);
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END COMPONENT;
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COMPONENT AD7688_spi_if IS
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GENERIC(ChanelCount : INTEGER);
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PORT(clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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DataReady : OUT STD_LOGIC;
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sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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smpout : OUT Samples(ChanelCount-1 DOWNTO 0)
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);
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END COMPONENT;
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--COMPONENT lpp_apb_ad_conv
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-- GENERIC(
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-- pindex : INTEGER := 0;
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-- paddr : INTEGER := 0;
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-- pmask : INTEGER := 16#fff#;
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-- pirq : INTEGER := 0;
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-- abits : INTEGER := 8;
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-- ChanelCount : INTEGER := 1;
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-- clkkHz : INTEGER := 50000;
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-- smpClkHz : INTEGER := 100;
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-- ADCref : INTEGER := AD7688);
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-- PORT (
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-- clk : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- apbi : IN apb_slv_in_type;
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-- apbo : OUT apb_slv_out_type;
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-- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- AD_out : OUT AD7688_out);
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--END COMPONENT;
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--COMPONENT ADS7886_drvr IS
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-- GENERIC(ChanelCount : INTEGER;
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-- clkkHz : INTEGER);
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-- PORT (
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-- clk : IN STD_LOGIC;
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-- reset : IN STD_LOGIC;
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-- smplClk : IN STD_LOGIC;
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-- DataReady : OUT STD_LOGIC;
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-- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
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-- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
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-- AD_out : OUT AD7688_out
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-- );
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--END COMPONENT;
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--COMPONENT WriteGen_ADC IS
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-- PORT(
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-- clk : IN STD_LOGIC;
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-- rstn : IN STD_LOGIC;
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-- SmplCLK : IN STD_LOGIC;
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-- DataReady : IN STD_LOGIC;
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-- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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-- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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-- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
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-- );
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--END COMPONENT;
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--===========================================================|
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--======================= ADS 127X =========================|
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--===========================================================|
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Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic;
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constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
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constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
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Type ADS127X_MODE_Type is array(1 downto 0) of std_logic;
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constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
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constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
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constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
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Type ADS127X_config is
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record
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SYNC : std_logic;
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CLKDIV : std_logic;
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FORMAT : ADS127X_FORMAT_Type;
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MODE : ADS127X_MODE_Type;
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end record;
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COMPONENT ADS1274_DRIVER is
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generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
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port(
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Clk : in std_logic;
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reset : in std_logic;
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SpiClk : out std_logic;
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DIN : in std_logic_vector(3 downto 0);
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Ready : in std_logic;
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Format : out std_logic_vector(2 downto 0);
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Mode : out std_logic_vector(1 downto 0);
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ClkDiv : out std_logic;
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PWDOWN : out std_logic_vector(3 downto 0);
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SmplClk : in std_logic;
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OUT0 : out std_logic_vector(23 downto 0);
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OUT1 : out std_logic_vector(23 downto 0);
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OUT2 : out std_logic_vector(23 downto 0);
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OUT3 : out std_logic_vector(23 downto 0);
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FSynch : out std_logic;
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test : out std_logic
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);
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end COMPONENT;
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-- todo clean file
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COMPONENT DUAL_ADS1278_DRIVER is
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port(
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Clk : in std_logic;
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reset : in std_logic;
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SpiClk : out std_logic;
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DIN : in std_logic_vector(1 downto 0);
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SmplClk : in std_logic;
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OUT00 : out std_logic_vector(23 downto 0);
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OUT01 : out std_logic_vector(23 downto 0);
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OUT02 : out std_logic_vector(23 downto 0);
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OUT03 : out std_logic_vector(23 downto 0);
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OUT04 : out std_logic_vector(23 downto 0);
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OUT05 : out std_logic_vector(23 downto 0);
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OUT06 : out std_logic_vector(23 downto 0);
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OUT07 : out std_logic_vector(23 downto 0);
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OUT10 : out std_logic_vector(23 downto 0);
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OUT11 : out std_logic_vector(23 downto 0);
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OUT12 : out std_logic_vector(23 downto 0);
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OUT13 : out std_logic_vector(23 downto 0);
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OUT14 : out std_logic_vector(23 downto 0);
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OUT15 : out std_logic_vector(23 downto 0);
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OUT16 : out std_logic_vector(23 downto 0);
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OUT17 : out std_logic_vector(23 downto 0);
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FSynch : out std_logic
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);
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end COMPONENT;
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END lpp_ad_conv;
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