HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd

MiniSpartan6:...

MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.

Alexis Jeandet - - Load All Authors

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             lpp_lfr_management_apbreg_pkg.vhd
        
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      LIBRARY ieee;

      USE ieee.std_logic_1164.ALL;

      USE ieee.numeric_std.ALL;

      PACKAGE lpp_lfr_management_apbreg_pkg IS

        CONSTANT ADDR_LFR_MANAGMENT_CONTROL          : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";

        CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";

        CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE      : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";

        CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";

        CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";

        CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";

        CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";

        CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL      : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";

        CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE          : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";

        CONSTANT ADDR_LFR_MANAGMENT_DAC_N            : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";

        CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT  : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";

        CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN      : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";

        CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA  : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";

      END lpp_lfr_management_apbreg_pkg;

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				LIBRARY ieee;
				USE ieee.std_logic_1164.ALL;
				USE ieee.numeric_std.ALL;

				PACKAGE lpp_lfr_management_apbreg_pkg IS

				CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
				CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
				CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
				CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
				CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
				CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
				CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
				CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
				CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
				CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
				CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
				CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
				CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";

				END lpp_lfr_management_apbreg_pkg;