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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:14:05 07/02/2012
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-- Design Name:
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-- Module Name: lfr_time_management - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.Clk_divider;
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ENTITY lfr_time_management IS
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GENERIC (
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masterclk : INTEGER := 25000000; -- master clock in Hz
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timeclk : INTEGER := 49152000; -- 2nd clock in Hz
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finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
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nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
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);
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PORT (
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master_clock : IN STD_LOGIC; --! Clock -- 25MHz
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time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz
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resetn : IN STD_LOGIC; --! Reset
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grspw_tick : IN STD_LOGIC;
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soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz
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coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
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fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
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next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
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-- reset_next_commutation : OUT STD_LOGIC;
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irq1 : OUT STD_LOGIC; -- 25MHz
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irq2 : OUT STD_LOGIC -- 25MHz
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);
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END lfr_time_management;
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ARCHITECTURE Behavioral OF lfr_time_management IS
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SIGNAL resetn_clk_div : STD_LOGIC;
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SIGNAL clk_div : STD_LOGIC;
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--
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SIGNAL flag : STD_LOGIC;
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SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL cpt : INTEGER RANGE 0 TO 100000;
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SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
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--
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SIGNAL sirq1 : STD_LOGIC;
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SIGNAL sirq2 : STD_LOGIC;
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SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
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SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL p_clk_div : STD_LOGIC;
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--
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TYPE state_type IS (auto, slave);
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SIGNAL state : state_type;
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TYPE timer_type IS (idle, engaged);
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SIGNAL commutation_timer : timer_type;
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BEGIN
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--*******************************************
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-- COMMUTATION TIMER AND INTERRUPT GENERATION
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PROCESS(master_clock, resetn)
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BEGIN
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IF resetn = '0' THEN
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commutation_timer <= idle;
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cpt_next_commutation <= 0;
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sirq1 <= '0';
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sirq2 <= '0';
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latched_next_commutation <= x"ffffffff";
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p_next_commutation <= (others => '0');
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p_clk_div <= '0';
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ELSIF master_clock'EVENT AND master_clock = '1' THEN
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CASE commutation_timer IS
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WHEN idle =>
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sirq1 <= '0';
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sirq2 <= '0';
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IF s_coarse_time = latched_next_commutation THEN
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commutation_timer <= engaged; -- transition to state "engaged"
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sirq1 <= '1'; -- start the pulse on sirq1
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latched_next_commutation <= x"ffffffff";
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ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
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latched_next_commutation <= next_commutation; -- latch the value
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ELSE
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commutation_timer <= idle;
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END IF;
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WHEN engaged =>
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sirq1 <= '0'; -- stop the pulse on sirq1
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IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
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IF cpt_next_commutation = 65536 THEN
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cpt_next_commutation <= 0;
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commutation_timer <= idle;
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sirq2 <= '1'; -- start the pulse on sirq2
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ELSE
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cpt_next_commutation <= cpt_next_commutation + 1;
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END IF;
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END IF;
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WHEN OTHERS =>
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commutation_timer <= idle;
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END CASE;
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p_next_commutation <= next_commutation;
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p_clk_div <= clk_div;
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END IF;
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END PROCESS;
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irq1 <= sirq1;
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irq2 <= sirq2;
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-- reset_next_commutation <= '0';
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--
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--*******************************************
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--**********************
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-- synchronization stage
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PROCESS(master_clock, resetn) -- resynchronisation with clk
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BEGIN
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IF resetn = '0' THEN
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coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
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ELSIF master_clock'EVENT AND master_clock = '1' THEN
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coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
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END IF;
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END PROCESS;
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--
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--**********************
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-- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
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PROCESS(clk_div, resetn) -- JC
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BEGIN
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IF resetn = '0' THEN
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flag <= '0';
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cpt <= 0;
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secondary_cpt <= 0;
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s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
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previous_coarse_time_load <= x"80000000";
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state <= auto;
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--ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
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-- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
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-- -- s_coarse_time <= coarse_time_load;
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-- -- flag <= '0';
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-- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
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-- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
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-- --END IF;
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-- cpt <= 0;
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-- secondary_cpt <= 0;
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-- state <= slave;
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ELSIF clk_div'EVENT AND clk_div = '1' THEN
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CASE state IS
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WHEN auto =>
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IF grspw_tick = '1' OR soft_tick = '1' THEN
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IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
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s_coarse_time <= coarse_time_load;
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ELSE -- if coarse_time_load has not changed, increment the value autonomously
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s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
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END IF;
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flag <= '0';
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cpt <= 0;
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secondary_cpt <= 0;
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state <= slave;
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ELSE
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IF cpt = 65535 THEN
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IF flag = '1' THEN
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s_coarse_time <= coarse_time_load;
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flag <= '0';
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ELSE
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s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
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END IF;
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cpt <= 0;
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secondary_cpt <= secondary_cpt + 1;
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ELSE
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cpt <= cpt + 1;
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END IF;
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END IF;
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WHEN slave =>
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IF grspw_tick = '1' OR soft_tick = '1' THEN
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IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
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s_coarse_time <= coarse_time_load;
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ELSE -- if coarse_time_load has not changed, increment the value autonomously
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s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
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END IF;
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flag <= '0';
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cpt <= 0;
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secondary_cpt <= 0;
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state <= slave;
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ELSE
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IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
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state <= auto; -- commutation to AUTO state
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IF flag = '1' THEN
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s_coarse_time <= coarse_time_load;
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flag <= '0';
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ELSE
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s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
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END IF;
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cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
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secondary_cpt <= secondary_cpt + 1;
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ELSE
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cpt <= cpt + 1;
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END IF;
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END IF;
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WHEN OTHERS =>
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state <= auto;
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END CASE;
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IF secondary_cpt > 60 THEN
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s_coarse_time(31) <= '1';
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END IF;
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IF NOT(previous_coarse_time_load = coarse_time_load) THEN
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flag <= '1';
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END IF;
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previous_coarse_time_load <= coarse_time_load;
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END IF;
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END PROCESS;
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fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
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-- resetn grspw_tick soft_tick resetn_clk_div
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-- 0 0 0 0
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-- 0 0 1 0
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-- 0 1 0 0
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-- 0 1 1 0
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-- 1 0 0 1
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-- 1 0 1 0
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-- 1 1 0 0
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-- 1 1 1 0
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resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
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Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
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GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
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END Behavioral;
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