HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r190:c9aa3c572bb2

saved

pellion -

r190:c9aa3c572bb2 JC

parent child

Context file:

r190:c9aa3c572bb2

Collapse all files

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +2 0

                   Cel_ongoing    <= 0;              --
                   sample_in_rot  <= '0';
+                  IIR_CEL_STATE <= waiting;
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   CASE IIR_CEL_STATE IS

lib/lpp/dsp/lpp_downsampling/Downsampling.vhd +6 -1

                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   counter        <= 0;
                   sample_out_val <= '0';
+                  all_sampl: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
+                  	all_bit: FOR J IN SampleSize-1 DOWNTO 0 LOOP
+            	        sample_out(I,J)     <= '0';
+                    END LOOP all_bit;
+                  END LOOP all_sampl;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF sample_in_val = '1' THEN
                     IF counter = 0 THEN
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +6 -6

               SIGNAL force_tick             : STD_LOGIC;
               SIGNAL previous_force_tick    : STD_LOGIC;
               SIGNAL soft_tick              : STD_LOGIC;
-              SIGNAL reset_next_commutation : STD_LOGIC;
+            --  SIGNAL reset_next_commutation : STD_LOGIC;
               SIGNAL irq1 : STD_LOGIC;
               SIGNAL irq2 : STD_LOGIC;
                   coarse_time => r.coarse_time,
                   fine_time => r.fine_time,
                   next_commutation => r.next_commutation,
-                  reset_next_commutation => reset_next_commutation,
+            --      reset_next_commutation => reset_next_commutation,
                   irq1             => irq1,--apbo.pirq(pirq),
                   irq2 => irq2);--apbo.pirq(pirq+1));
               --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
               --END GENERATE all_irq_sig;
-              PROCESS(resetn, clk25MHz, reset_next_commutation)
+              PROCESS(resetn, clk25MHz)--, reset_next_commutation)
               BEGIN
                 IF resetn = '0' THEN
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
-                ELSIF reset_next_commutation = '1' THEN
+                --ELSIF reset_next_commutation = '1' THEN
-                  r.next_commutation <= x"ffffffff";
+                --  r.next_commutation <= x"ffffffff";
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

lib/lpp/lfr_time_management/lfr_time_management.vhd +15 -14

                 nb_clk_div_ticks : INTEGER := 1  -- nb ticks before commutation to AUTO state
                 );
               PORT (
-                master_clock           : IN  STD_LOGIC;  --! Clock
+                master_clock           : IN  STD_LOGIC;  --! Clock                                  -- 25MHz
-                time_clock             : IN  STD_LOGIC;  --! 2nd Clock
+                time_clock             : IN  STD_LOGIC;  --! 2nd Clock                              -- 49MHz
                 resetn                 : IN  STD_LOGIC;  --! Reset
                 grspw_tick             : IN  STD_LOGIC;
-                soft_tick              : IN  STD_LOGIC;  --! soft tick, load the coarse_time value
+                soft_tick              : IN  STD_LOGIC;  --! soft tick, load the coarse_time value  -- 25MHz
-                coarse_time_load       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                coarse_time_load       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);                         -- 25MHz
-                coarse_time            : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                coarse_time            : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);                         -- 25MHz
-                fine_time              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                fine_time              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);                         -- 25MHz
-                next_commutation       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                next_commutation       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);                         -- 25MHz
-                reset_next_commutation : OUT STD_LOGIC;
+            --    reset_next_commutation : OUT STD_LOGIC;
-                irq1                   : OUT STD_LOGIC;
+                irq1                   : OUT STD_LOGIC;                                             -- 25MHz
-                irq2                   : OUT STD_LOGIC
+                irq2                   : OUT STD_LOGIC                                              -- 25MHz
                 );
             END lfr_time_management;
                   sirq1                    <= '0';
                   sirq2                    <= '0';
                   latched_next_commutation <= x"ffffffff";
+                  p_next_commutation       <= (others => '0');
+                  p_clk_div                <= '0';
                 ELSIF master_clock'EVENT AND master_clock = '1' THEN
                   CASE commutation_timer IS
               irq1                   <= sirq1;
               irq2                   <= sirq2;
-              reset_next_commutation <= '0';
+            --  reset_next_commutation <= '0';
             --
             --*******************************************

lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +1 -1

             		coarse_time			: out   std_logic_vector(31 downto 0);
             		fine_time			: out	std_logic_vector(31 downto 0);
             		next_commutation	: in	std_logic_vector(31 downto 0);
-            		reset_next_commutation: out  std_logic;
+            --		reset_next_commutation: out  std_logic;
             		irq1                : out std_logic;
             		irq2                : out std_logic
             		);

lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +2 0

                 IF rstn = '0' THEN
                   FOR l IN 0 TO ChanelCount-1 LOOP
                     shift_reg(l) <= (OTHERS => '0');
+            	    sample(l)(15 DOWNTO 0)           <= (OTHERS => '0');
                   END LOOP;
                   sample_bit_counter <= 0;
                   sample_val         <= '0';
                   SCK                <= '1';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF cnv_run_sync = '0' THEN

lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +16 0

@@ -107,6 +107,22 COMPONENT RHF1401_drvr IS
107	);	107	);
108	END COMPONENT;	108	END COMPONENT;
109		109
		110	COMPONENT AD7688_drvr_sync
		111	GENERIC (
		112	ChanelCount : INTEGER;
		113	ncycle_cnv_high : INTEGER;
		114	ncycle_cnv : INTEGER);
		115	PORT (
		116	cnv_clk : IN STD_LOGIC;
		117	cnv_rstn : IN STD_LOGIC;
		118	cnv_run : IN STD_LOGIC;
		119	cnv : OUT STD_LOGIC;
		120	sck : OUT STD_LOGIC;
		121	sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
		122	sample : OUT Samples(ChanelCount-1 DOWNTO 0);
		123	sample_val : OUT STD_LOGIC);
		124	END COMPONENT;
		125
110	--COMPONENT AD7688_drvr IS	126	--COMPONENT AD7688_drvr IS
111	-- GENERIC(ChanelCount : INTEGER;	127	-- GENERIC(ChanelCount : INTEGER;
112	-- clkkHz : INTEGER);	128	-- clkkHz : INTEGER);

lib/lpp/lpp_ad_Conv/vhdlsyn.txt +1 0

             lpp_ad_Conv.vhd
             AD7688_drvr.vhd
+            AD7688_drvr_sync.vhd
             WriteGen_ADC.vhd
             TestModule_ADS7886.vhd

lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +5 -2

                   send_ok <= '0';
                   send_ko <= '0';
-                  DMAIn.Reset   <= '0';
+                  DMAIn.Reset   <= '1';
                   DMAIn.Address <= (OTHERS => '0');
                   DMAIn.Request <= '0';
                   DMAIn.Store   <= '0';
                   DMAIn.Burst   <= '1';
                   DMAIn.Lock    <= '0';
                   data_counter  <= 0;
+                  grant_counter <= 0;
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
+                  DMAIn.Reset   <= '0';
                   CASE state IS
                     WHEN IDLE =>
                       DMAIn.Store   <= '1';
                      '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
                      '1';
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +407 -407

This diff has been collapsed as it changes many lines, (814 lines changed) Show them Hide them
	@@ -1,408 +1,408
	1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com	21	-- jean-christophe.pellion@easii-ic.com
	22	----------------------------------------------------------------------------	22	----------------------------------------------------------------------------
	23	LIBRARY ieee;	23	LIBRARY ieee;
	24	USE ieee.std_logic_1164.ALL;	24	USE ieee.std_logic_1164.ALL;
	25	USE ieee.numeric_std.ALL;	25	USE ieee.numeric_std.ALL;
	26	LIBRARY grlib;	26	LIBRARY grlib;
	27	USE grlib.amba.ALL;	27	USE grlib.amba.ALL;
	28	USE grlib.stdlib.ALL;	28	USE grlib.stdlib.ALL;
	29	USE grlib.devices.ALL;	29	USE grlib.devices.ALL;
	30	LIBRARY lpp;	30	LIBRARY lpp;
	31	USE lpp.lpp_amba.ALL;	31	USE lpp.lpp_amba.ALL;
	32	USE lpp.apb_devices_list.ALL;	32	USE lpp.apb_devices_list.ALL;
	33	USE lpp.lpp_memory.ALL;	33	USE lpp.lpp_memory.ALL;
	34	LIBRARY techmap;	34	LIBRARY techmap;
	35	USE techmap.gencomp.ALL;	35	USE techmap.gencomp.ALL;
	36		36
	37	ENTITY lpp_top_apbreg IS	37	ENTITY lpp_top_apbreg IS
	38	GENERIC (	38	GENERIC (
	39	nb_burst_available_size : INTEGER := 11;	39	nb_burst_available_size : INTEGER := 11;
	40	nb_snapshot_param_size : INTEGER := 11;	40	nb_snapshot_param_size : INTEGER := 11;
	41	delta_snapshot_size : INTEGER := 16;	41	delta_snapshot_size : INTEGER := 16;
	42	delta_f2_f0_size : INTEGER := 10;	42	delta_f2_f0_size : INTEGER := 10;
	43	delta_f2_f1_size : INTEGER := 10;	43	delta_f2_f1_size : INTEGER := 10;
	44		44
	45	pindex : INTEGER := 4;	45	pindex : INTEGER := 4;
	46	paddr : INTEGER := 4;	46	paddr : INTEGER := 4;
	47	pmask : INTEGER := 16#fff#;	47	pmask : INTEGER := 16#fff#;
	48	pirq : INTEGER := 0);	48	pirq : INTEGER := 0);
	49	PORT (	49	PORT (
	50	-- AMBA AHB system signals	50	-- AMBA AHB system signals
	51	HCLK : IN STD_ULOGIC;	51	HCLK : IN STD_ULOGIC;
	52	HRESETn : IN STD_ULOGIC;	52	HRESETn : IN STD_ULOGIC;
	53		53
	54	-- AMBA APB Slave Interface	54	-- AMBA APB Slave Interface
	55	apbi : IN apb_slv_in_type;	55	apbi : IN apb_slv_in_type;
	56	apbo : OUT apb_slv_out_type;	56	apbo : OUT apb_slv_out_type;
	57		57
	58	---------------------------------------------------------------------------	58	---------------------------------------------------------------------------
	59	-- Spectral Matrix Reg	59	-- Spectral Matrix Reg
	60	-- IN	60	-- IN
	61	ready_matrix_f0_0 : IN STD_LOGIC;	61	ready_matrix_f0_0 : IN STD_LOGIC;
	62	ready_matrix_f0_1 : IN STD_LOGIC;	62	ready_matrix_f0_1 : IN STD_LOGIC;
	63	ready_matrix_f1 : IN STD_LOGIC;	63	ready_matrix_f1 : IN STD_LOGIC;
	64	ready_matrix_f2 : IN STD_LOGIC;	64	ready_matrix_f2 : IN STD_LOGIC;
	65	error_anticipating_empty_fifo : IN STD_LOGIC;	65	error_anticipating_empty_fifo : IN STD_LOGIC;
	66	error_bad_component_error : IN STD_LOGIC;	66	error_bad_component_error : IN STD_LOGIC;
	67	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	67	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	68		68
	69	-- OUT	69	-- OUT
	70	status_ready_matrix_f0_0 : OUT STD_LOGIC;	70	status_ready_matrix_f0_0 : OUT STD_LOGIC;
	71	status_ready_matrix_f0_1 : OUT STD_LOGIC;	71	status_ready_matrix_f0_1 : OUT STD_LOGIC;
	72	status_ready_matrix_f1 : OUT STD_LOGIC;	72	status_ready_matrix_f1 : OUT STD_LOGIC;
	73	status_ready_matrix_f2 : OUT STD_LOGIC;	73	status_ready_matrix_f2 : OUT STD_LOGIC;
	74	status_error_anticipating_empty_fifo : OUT STD_LOGIC;	74	status_error_anticipating_empty_fifo : OUT STD_LOGIC;
	75	status_error_bad_component_error : OUT STD_LOGIC;	75	status_error_bad_component_error : OUT STD_LOGIC;
	76		76
	77	config_active_interruption_onNewMatrix : OUT STD_LOGIC;	77	config_active_interruption_onNewMatrix : OUT STD_LOGIC;
	78	config_active_interruption_onError : OUT STD_LOGIC;	78	config_active_interruption_onError : OUT STD_LOGIC;
	79	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	79	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	80	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	80	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	81	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	81	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	82	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	82	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	83	---------------------------------------------------------------------------	83	---------------------------------------------------------------------------
	84	---------------------------------------------------------------------------	84	---------------------------------------------------------------------------
	85	-- WaveForm picker Reg	85	-- WaveForm picker Reg
	86	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	86	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	87	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	87	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	88	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	88	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	89	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	89	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	90		90
	91	-- OUT	91	-- OUT
	92	data_shaping_BW : OUT STD_LOGIC;	92	data_shaping_BW : OUT STD_LOGIC;
	93	data_shaping_SP0 : OUT STD_LOGIC;	93	data_shaping_SP0 : OUT STD_LOGIC;
	94	data_shaping_SP1 : OUT STD_LOGIC;	94	data_shaping_SP1 : OUT STD_LOGIC;
	95	data_shaping_R0 : OUT STD_LOGIC;	95	data_shaping_R0 : OUT STD_LOGIC;
	96	data_shaping_R1 : OUT STD_LOGIC;	96	data_shaping_R1 : OUT STD_LOGIC;
	97		97
	98	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);	98	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
	99	delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);	99	delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
	100	delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);	100	delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
	101	nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);	101	nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
	102	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	102	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	103		103
	104	enable_f0 : OUT STD_LOGIC;	104	enable_f0 : OUT STD_LOGIC;
	105	enable_f1 : OUT STD_LOGIC;	105	enable_f1 : OUT STD_LOGIC;
	106	enable_f2 : OUT STD_LOGIC;	106	enable_f2 : OUT STD_LOGIC;
	107	enable_f3 : OUT STD_LOGIC;	107	enable_f3 : OUT STD_LOGIC;
	108		108
	109	burst_f0 : OUT STD_LOGIC;	109	burst_f0 : OUT STD_LOGIC;
	110	burst_f1 : OUT STD_LOGIC;	110	burst_f1 : OUT STD_LOGIC;
	111	burst_f2 : OUT STD_LOGIC;	111	burst_f2 : OUT STD_LOGIC;
	112		112
	113	addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	113	addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	114	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	114	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	115	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	115	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	116	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)	116	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
	117		117
	118	---------------------------------------------------------------------------	118	---------------------------------------------------------------------------
	119	);	119	);
	120		120
	121	END lpp_top_apbreg;	121	END lpp_top_apbreg;
	122		122
	123	ARCHITECTURE beh OF lpp_top_apbreg IS	123	ARCHITECTURE beh OF lpp_top_apbreg IS
	124		124
	125	CONSTANT REVISION : INTEGER := 1;	125	CONSTANT REVISION : INTEGER := 1;
	126		126
	127	CONSTANT pconfig : apb_config_type := (	127	CONSTANT pconfig : apb_config_type := (
	128	0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 10, REVISION, pirq),	128	0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq),
	129	1 => apb_iobar(paddr, pmask));	129	1 => apb_iobar(paddr, pmask));
	130		130
	131	TYPE lpp_SpectralMatrix_regs IS RECORD	131	TYPE lpp_SpectralMatrix_regs IS RECORD
	132	config_active_interruption_onNewMatrix : STD_LOGIC;	132	config_active_interruption_onNewMatrix : STD_LOGIC;
	133	config_active_interruption_onError : STD_LOGIC;	133	config_active_interruption_onError : STD_LOGIC;
	134	status_ready_matrix_f0_0 : STD_LOGIC;	134	status_ready_matrix_f0_0 : STD_LOGIC;
	135	status_ready_matrix_f0_1 : STD_LOGIC;	135	status_ready_matrix_f0_1 : STD_LOGIC;
	136	status_ready_matrix_f1 : STD_LOGIC;	136	status_ready_matrix_f1 : STD_LOGIC;
	137	status_ready_matrix_f2 : STD_LOGIC;	137	status_ready_matrix_f2 : STD_LOGIC;
	138	status_error_anticipating_empty_fifo : STD_LOGIC;	138	status_error_anticipating_empty_fifo : STD_LOGIC;
	139	status_error_bad_component_error : STD_LOGIC;	139	status_error_bad_component_error : STD_LOGIC;
	140	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	140	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	141	addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	141	addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	142	addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	142	addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	143	addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	143	addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	144	END RECORD;	144	END RECORD;
	145	SIGNAL reg_sp : lpp_SpectralMatrix_regs;	145	SIGNAL reg_sp : lpp_SpectralMatrix_regs;
	146		146
	147	TYPE lpp_WaveformPicker_regs IS RECORD	147	TYPE lpp_WaveformPicker_regs IS RECORD
	148	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);	148	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
	149	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	149	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	150	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	150	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	151	data_shaping_BW : STD_LOGIC;	151	data_shaping_BW : STD_LOGIC;
	152	data_shaping_SP0 : STD_LOGIC;	152	data_shaping_SP0 : STD_LOGIC;
	153	data_shaping_SP1 : STD_LOGIC;	153	data_shaping_SP1 : STD_LOGIC;
	154	data_shaping_R0 : STD_LOGIC;	154	data_shaping_R0 : STD_LOGIC;
	155	data_shaping_R1 : STD_LOGIC;	155	data_shaping_R1 : STD_LOGIC;
	156	delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);	156	delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
	157	delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);	157	delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
	158	delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);	158	delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
	159	nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);	159	nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
	160	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	160	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	161	enable_f0 : STD_LOGIC;	161	enable_f0 : STD_LOGIC;
	162	enable_f1 : STD_LOGIC;	162	enable_f1 : STD_LOGIC;
	163	enable_f2 : STD_LOGIC;	163	enable_f2 : STD_LOGIC;
	164	enable_f3 : STD_LOGIC;	164	enable_f3 : STD_LOGIC;
	165	burst_f0 : STD_LOGIC;	165	burst_f0 : STD_LOGIC;
	166	burst_f1 : STD_LOGIC;	166	burst_f1 : STD_LOGIC;
	167	burst_f2 : STD_LOGIC;	167	burst_f2 : STD_LOGIC;
	168	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	168	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	169	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	169	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	170	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	170	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	171	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);	171	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	172	END RECORD;	172	END RECORD;
	173	SIGNAL reg_wp : lpp_WaveformPicker_regs;	173	SIGNAL reg_wp : lpp_WaveformPicker_regs;
	174		174
	175	SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);	175	SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	176		176
	177	BEGIN -- beh	177	BEGIN -- beh
	178		178
	179	status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;	179	status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
	180	status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;	180	status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
	181	status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;	181	status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
	182	status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;	182	status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
	183	status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;	183	status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
	184	status_error_bad_component_error <= reg_sp.status_error_bad_component_error;	184	status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
	185		185
	186	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;	186	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
	187	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;	187	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
	188	addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;	188	addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
	189	addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;	189	addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
	190	addr_matrix_f1 <= reg_sp.addr_matrix_f1;	190	addr_matrix_f1 <= reg_sp.addr_matrix_f1;
	191	addr_matrix_f2 <= reg_sp.addr_matrix_f2;	191	addr_matrix_f2 <= reg_sp.addr_matrix_f2;
	192		192
	193		193
	194		194
	195		195
	196	data_shaping_BW <= reg_wp.data_shaping_BW;	196	data_shaping_BW <= reg_wp.data_shaping_BW;
	197	data_shaping_SP0 <= reg_wp.data_shaping_SP0;	197	data_shaping_SP0 <= reg_wp.data_shaping_SP0;
	198	data_shaping_SP1 <= reg_wp.data_shaping_SP1;	198	data_shaping_SP1 <= reg_wp.data_shaping_SP1;
	199	data_shaping_R0 <= reg_wp.data_shaping_R0;	199	data_shaping_R0 <= reg_wp.data_shaping_R0;
	200	data_shaping_R1 <= reg_wp.data_shaping_R1;	200	data_shaping_R1 <= reg_wp.data_shaping_R1;
	201		201
	202	delta_snapshot <= reg_wp.delta_snapshot;	202	delta_snapshot <= reg_wp.delta_snapshot;
	203	delta_f2_f1 <= reg_wp.delta_f2_f1;	203	delta_f2_f1 <= reg_wp.delta_f2_f1;
	204	delta_f2_f0 <= reg_wp.delta_f2_f0;	204	delta_f2_f0 <= reg_wp.delta_f2_f0;
	205	nb_burst_available <= reg_wp.nb_burst_available;	205	nb_burst_available <= reg_wp.nb_burst_available;
	206	nb_snapshot_param <= reg_wp.nb_snapshot_param;	206	nb_snapshot_param <= reg_wp.nb_snapshot_param;
	207		207
	208	enable_f0 <= reg_wp.enable_f0;	208	enable_f0 <= reg_wp.enable_f0;
	209	enable_f1 <= reg_wp.enable_f1;	209	enable_f1 <= reg_wp.enable_f1;
	210	enable_f2 <= reg_wp.enable_f2;	210	enable_f2 <= reg_wp.enable_f2;
	211	enable_f3 <= reg_wp.enable_f3;	211	enable_f3 <= reg_wp.enable_f3;
	212		212
	213	burst_f0 <= reg_wp.burst_f0;	213	burst_f0 <= reg_wp.burst_f0;
	214	burst_f1 <= reg_wp.burst_f1;	214	burst_f1 <= reg_wp.burst_f1;
	215	burst_f2 <= reg_wp.burst_f2;	215	burst_f2 <= reg_wp.burst_f2;
	216		216
	217	addr_data_f0 <= reg_wp.addr_data_f0;	217	addr_data_f0 <= reg_wp.addr_data_f0;
	218	addr_data_f1 <= reg_wp.addr_data_f1;	218	addr_data_f1 <= reg_wp.addr_data_f1;
	219	addr_data_f2 <= reg_wp.addr_data_f2;	219	addr_data_f2 <= reg_wp.addr_data_f2;
	220	addr_data_f3 <= reg_wp.addr_data_f3;	220	addr_data_f3 <= reg_wp.addr_data_f3;
	221		221
	222	lpp_top_apbreg : PROCESS (HCLK, HRESETn)	222	lpp_top_apbreg : PROCESS (HCLK, HRESETn)
	223	VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);	223	VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
	224	BEGIN -- PROCESS lpp_dma_top	224	BEGIN -- PROCESS lpp_dma_top
	225	IF HRESETn = '0' THEN -- asynchronous reset (active low)	225	IF HRESETn = '0' THEN -- asynchronous reset (active low)
	226	reg_sp.config_active_interruption_onNewMatrix <= '0';	226	reg_sp.config_active_interruption_onNewMatrix <= '0';
	227	reg_sp.config_active_interruption_onError <= '0';	227	reg_sp.config_active_interruption_onError <= '0';
	228	reg_sp.status_ready_matrix_f0_0 <= '0';	228	reg_sp.status_ready_matrix_f0_0 <= '0';
	229	reg_sp.status_ready_matrix_f0_1 <= '0';	229	reg_sp.status_ready_matrix_f0_1 <= '0';
	230	reg_sp.status_ready_matrix_f1 <= '0';	230	reg_sp.status_ready_matrix_f1 <= '0';
	231	reg_sp.status_ready_matrix_f2 <= '0';	231	reg_sp.status_ready_matrix_f2 <= '0';
	232	reg_sp.status_error_anticipating_empty_fifo <= '0';	232	reg_sp.status_error_anticipating_empty_fifo <= '0';
	233	reg_sp.status_error_bad_component_error <= '0';	233	reg_sp.status_error_bad_component_error <= '0';
	234	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');	234	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
	235	reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');	235	reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
	236	reg_sp.addr_matrix_f1 <= (OTHERS => '0');	236	reg_sp.addr_matrix_f1 <= (OTHERS => '0');
	237	reg_sp.addr_matrix_f2 <= (OTHERS => '0');	237	reg_sp.addr_matrix_f2 <= (OTHERS => '0');
	238	prdata <= (OTHERS => '0');	238	prdata <= (OTHERS => '0');
	239		239
	240	apbo.pirq <= (OTHERS => '0');	240	apbo.pirq <= (OTHERS => '0');
	241		241
	242	status_full_ack <= (OTHERS => '0');	242	status_full_ack <= (OTHERS => '0');
	243		243
	244	reg_wp.data_shaping_BW <= '0';	244	reg_wp.data_shaping_BW <= '0';
	245	reg_wp.data_shaping_SP0 <= '0';	245	reg_wp.data_shaping_SP0 <= '0';
	246	reg_wp.data_shaping_SP1 <= '0';	246	reg_wp.data_shaping_SP1 <= '0';
	247	reg_wp.data_shaping_R0 <= '0';	247	reg_wp.data_shaping_R0 <= '0';
	248	reg_wp.data_shaping_R1 <= '0';	248	reg_wp.data_shaping_R1 <= '0';
	249	reg_wp.enable_f0 <= '0';	249	reg_wp.enable_f0 <= '0';
	250	reg_wp.enable_f1 <= '0';	250	reg_wp.enable_f1 <= '0';
	251	reg_wp.enable_f2 <= '0';	251	reg_wp.enable_f2 <= '0';
	252	reg_wp.enable_f3 <= '0';	252	reg_wp.enable_f3 <= '0';
	253	reg_wp.burst_f0 <= '0';	253	reg_wp.burst_f0 <= '0';
	254	reg_wp.burst_f1 <= '0';	254	reg_wp.burst_f1 <= '0';
	255	reg_wp.burst_f2 <= '0';	255	reg_wp.burst_f2 <= '0';
	256	reg_wp.addr_data_f0 <= (OTHERS => '0');	256	reg_wp.addr_data_f0 <= (OTHERS => '0');
	257	reg_wp.addr_data_f1 <= (OTHERS => '0');	257	reg_wp.addr_data_f1 <= (OTHERS => '0');
	258	reg_wp.addr_data_f2 <= (OTHERS => '0');	258	reg_wp.addr_data_f2 <= (OTHERS => '0');
	259	reg_wp.addr_data_f3 <= (OTHERS => '0');	259	reg_wp.addr_data_f3 <= (OTHERS => '0');
	260	reg_wp.status_full <= (OTHERS => '0');	260	reg_wp.status_full <= (OTHERS => '0');
	261	reg_wp.status_full_err <= (OTHERS => '0');	261	reg_wp.status_full_err <= (OTHERS => '0');
	262	reg_wp.status_new_err <= (OTHERS => '0');	262	reg_wp.status_new_err <= (OTHERS => '0');
	263	reg_wp.delta_snapshot <= (OTHERS => '0');	263	reg_wp.delta_snapshot <= (OTHERS => '0');
	264	reg_wp.delta_f2_f1 <= (OTHERS => '0');	264	reg_wp.delta_f2_f1 <= (OTHERS => '0');
	265	reg_wp.delta_f2_f0 <= (OTHERS => '0');	265	reg_wp.delta_f2_f0 <= (OTHERS => '0');
	266	reg_wp.nb_burst_available <= (OTHERS => '0');	266	reg_wp.nb_burst_available <= (OTHERS => '0');
	267	reg_wp.nb_snapshot_param <= (OTHERS => '0');	267	reg_wp.nb_snapshot_param <= (OTHERS => '0');
	268		268
	269	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge	269	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
	270	status_full_ack <= (OTHERS => '0');	270	status_full_ack <= (OTHERS => '0');
	271		271
	272	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;	272	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
	273	reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;	273	reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
	274	reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;	274	reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
	275	reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;	275	reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
	276		276
	277	reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;	277	reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
	278	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;	278	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
	279		279
	280	reg_wp.status_full <= reg_wp.status_full OR status_full;	280	reg_wp.status_full <= reg_wp.status_full OR status_full;
	281	reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;	281	reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
	282	reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;	282	reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
	283		283
	284	paddr := "000000";	284	paddr := "000000";
	285	paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);	285	paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
	286	prdata <= (OTHERS => '0');	286	prdata <= (OTHERS => '0');
	287	IF apbi.psel(pindex) = '1' THEN	287	IF apbi.psel(pindex) = '1' THEN
	288	-- APB DMA READ --	288	-- APB DMA READ --
	289	CASE paddr(7 DOWNTO 2) IS	289	CASE paddr(7 DOWNTO 2) IS
	290	--	290	--
	291	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;	291	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
	292	prdata(1) <= reg_sp.config_active_interruption_onError;	292	prdata(1) <= reg_sp.config_active_interruption_onError;
	293	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;	293	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
	294	prdata(1) <= reg_sp.status_ready_matrix_f0_1;	294	prdata(1) <= reg_sp.status_ready_matrix_f0_1;
	295	prdata(2) <= reg_sp.status_ready_matrix_f1;	295	prdata(2) <= reg_sp.status_ready_matrix_f1;
	296	prdata(3) <= reg_sp.status_ready_matrix_f2;	296	prdata(3) <= reg_sp.status_ready_matrix_f2;
	297	prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;	297	prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
	298	prdata(5) <= reg_sp.status_error_bad_component_error;	298	prdata(5) <= reg_sp.status_error_bad_component_error;
	299	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;	299	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
	300	WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;	300	WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
	301	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;	301	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
	302	WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;	302	WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
	303	WHEN "000110" => prdata <= debug_reg;	303	WHEN "000110" => prdata <= debug_reg;
	304	--	304	--
	305	WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;	305	WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
	306	prdata(1) <= reg_wp.data_shaping_SP0;	306	prdata(1) <= reg_wp.data_shaping_SP0;
	307	prdata(2) <= reg_wp.data_shaping_SP1;	307	prdata(2) <= reg_wp.data_shaping_SP1;
	308	prdata(3) <= reg_wp.data_shaping_R0;	308	prdata(3) <= reg_wp.data_shaping_R0;
	309	prdata(4) <= reg_wp.data_shaping_R1;	309	prdata(4) <= reg_wp.data_shaping_R1;
	310	WHEN "001001" => prdata(0) <= reg_wp.enable_f0;	310	WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
	311	prdata(1) <= reg_wp.enable_f1;	311	prdata(1) <= reg_wp.enable_f1;
	312	prdata(2) <= reg_wp.enable_f2;	312	prdata(2) <= reg_wp.enable_f2;
	313	prdata(3) <= reg_wp.enable_f3;	313	prdata(3) <= reg_wp.enable_f3;
	314	prdata(4) <= reg_wp.burst_f0;	314	prdata(4) <= reg_wp.burst_f0;
	315	prdata(5) <= reg_wp.burst_f1;	315	prdata(5) <= reg_wp.burst_f1;
	316	prdata(6) <= reg_wp.burst_f2;	316	prdata(6) <= reg_wp.burst_f2;
	317	WHEN "001010" => prdata <= reg_wp.addr_data_f0;	317	WHEN "001010" => prdata <= reg_wp.addr_data_f0;
	318	WHEN "001011" => prdata <= reg_wp.addr_data_f1;	318	WHEN "001011" => prdata <= reg_wp.addr_data_f1;
	319	WHEN "001100" => prdata <= reg_wp.addr_data_f2;	319	WHEN "001100" => prdata <= reg_wp.addr_data_f2;
	320	WHEN "001101" => prdata <= reg_wp.addr_data_f3;	320	WHEN "001101" => prdata <= reg_wp.addr_data_f3;
	321	WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;	321	WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
	322	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;	322	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
	323	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;	323	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
	324	WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;	324	WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
	325	WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;	325	WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
	326	WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;	326	WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
	327	WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;	327	WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
	328	WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;	328	WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
	329	--	329	--
	330	WHEN OTHERS => NULL;	330	WHEN OTHERS => NULL;
	331	END CASE;	331	END CASE;
	332	IF (apbi.pwrite AND apbi.penable) = '1' THEN	332	IF (apbi.pwrite AND apbi.penable) = '1' THEN
	333	-- APB DMA WRITE --	333	-- APB DMA WRITE --
	334	CASE paddr(7 DOWNTO 2) IS	334	CASE paddr(7 DOWNTO 2) IS
	335	--	335	--
	336	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);	336	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
	337	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);	337	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
	338	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);	338	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
	339	reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);	339	reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
	340	reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);	340	reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
	341	reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);	341	reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
	342	reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);	342	reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
	343	reg_sp.status_error_bad_component_error <= apbi.pwdata(5);	343	reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
	344	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;	344	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
	345	WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;	345	WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
	346	WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;	346	WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
	347	WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;	347	WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
	348	--	348	--
	349	WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);	349	WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
	350	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);	350	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
	351	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);	351	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
	352	reg_wp.data_shaping_R0 <= apbi.pwdata(3);	352	reg_wp.data_shaping_R0 <= apbi.pwdata(3);
	353	reg_wp.data_shaping_R1 <= apbi.pwdata(4);	353	reg_wp.data_shaping_R1 <= apbi.pwdata(4);
	354	WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);	354	WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
	355	reg_wp.enable_f1 <= apbi.pwdata(1);	355	reg_wp.enable_f1 <= apbi.pwdata(1);
	356	reg_wp.enable_f2 <= apbi.pwdata(2);	356	reg_wp.enable_f2 <= apbi.pwdata(2);
	357	reg_wp.enable_f3 <= apbi.pwdata(3);	357	reg_wp.enable_f3 <= apbi.pwdata(3);
	358	reg_wp.burst_f0 <= apbi.pwdata(4);	358	reg_wp.burst_f0 <= apbi.pwdata(4);
	359	reg_wp.burst_f1 <= apbi.pwdata(5);	359	reg_wp.burst_f1 <= apbi.pwdata(5);
	360	reg_wp.burst_f2 <= apbi.pwdata(6);	360	reg_wp.burst_f2 <= apbi.pwdata(6);
	361	WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;	361	WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
	362	WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;	362	WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
	363	WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;	363	WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
	364	WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;	364	WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
	365	WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);	365	WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
	366	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);	366	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
	367	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);	367	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
	368	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);	368	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
	369	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);	369	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
	370	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);	370	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
	371	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);	371	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
	372	WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);	372	WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
	373	WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);	373	WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
	374	WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);	374	WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
	375	WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);	375	WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
	376	WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);	376	WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
	377	--	377	--
	378	WHEN OTHERS => NULL;	378	WHEN OTHERS => NULL;
	379	END CASE;	379	END CASE;
	380	END IF;	380	END IF;
	381	END IF;	381	END IF;
	382		382
	383	apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR	383	apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
	384	ready_matrix_f0_1 OR	384	ready_matrix_f0_1 OR
	385	ready_matrix_f1 OR	385	ready_matrix_f1 OR
	386	ready_matrix_f2)	386	ready_matrix_f2)
	387	)	387	)
	388	OR	388	OR
	389	(reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR	389	(reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
	390	error_bad_component_error)	390	error_bad_component_error)
	391	)	391	)
	392	OR	392	OR
	393	(status_full(0) OR status_full_err(0) OR status_new_err(0) OR	393	(status_full(0) OR status_full_err(0) OR status_new_err(0) OR
	394	status_full(1) OR status_full_err(1) OR status_new_err(1) OR	394	status_full(1) OR status_full_err(1) OR status_new_err(1) OR
	395	status_full(2) OR status_full_err(2) OR status_new_err(2) OR	395	status_full(2) OR status_full_err(2) OR status_new_err(2) OR
	396	status_full(3) OR status_full_err(3) OR status_new_err(3)	396	status_full(3) OR status_full_err(3) OR status_new_err(3)
	397	);	397	);
	398		398
	399		399
	400	END IF;	400	END IF;
	401	END PROCESS lpp_top_apbreg;	401	END PROCESS lpp_top_apbreg;
	402		402
	403	apbo.pindex <= pindex;	403	apbo.pindex <= pindex;
	404	apbo.pconfig <= pconfig;	404	apbo.pconfig <= pconfig;
	405	apbo.prdata <= prdata;	405	apbo.prdata <= prdata;
	406		406
	407		407
	408	END beh; No newline at end of file	408	END beh;

lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +57 -5

@@ -119,7 +119,8 PACKAGE lpp_top_lfr_pkg IS
119	nb_snapshot_param_size : INTEGER;	119	nb_snapshot_param_size : INTEGER;
120	delta_snapshot_size : INTEGER;	120	delta_snapshot_size : INTEGER;
121	delta_f2_f0_size : INTEGER;	121	delta_f2_f0_size : INTEGER;
122	delta_f2_f1_size : INTEGER);	122	delta_f2_f1_size : INTEGER;
		123	ENABLE_FILTER : STD_LOGIC);
123	PORT (	124	PORT (
124	cnv_run : IN STD_LOGIC;	125	cnv_run : IN STD_LOGIC;
125	cnv : OUT STD_LOGIC;	126	cnv : OUT STD_LOGIC;
@@ -149,10 +150,61 PACKAGE lpp_top_lfr_pkg IS
149	tech : INTEGER;	150	tech : INTEGER;
150	Mem_use : INTEGER);	151	Mem_use : INTEGER);
151	PORT (	152	PORT (
152	cnv_run : IN STD_LOGIC;	153	sample : IN Samples(7 DOWNTO 0);
153	~~cnv~~ : ~~OUT~~ STD_LOGIC;	154	sample_val : IN STD_LOGIC;
154	~~sck~~ : ~~OUT~~ STD_LOGIC;	155	cnv_clk : IN STD_LOGIC;
155	~~sdo~~ : IN STD_LOGIC~~_VECTOR~~(7 ~~DOWNTO~~ 0);	156	cnv_rstn : IN STD_LOGIC;
		157	clk : IN STD_LOGIC;
		158	rstn : IN STD_LOGIC;
		159	sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		160	sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		161	sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		162	sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		163	sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		164	sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		165	sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		166	sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		167	AHB_Master_In : IN AHB_Mst_In_Type;
		168	AHB_Master_Out : OUT AHB_Mst_Out_Type;
		169	coarse_time_0 : IN STD_LOGIC;
		170	data_shaping_SP0 : IN STD_LOGIC;
		171	data_shaping_SP1 : IN STD_LOGIC;
		172	data_shaping_R0 : IN STD_LOGIC;
		173	data_shaping_R1 : IN STD_LOGIC;
		174	delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
		175	delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
		176	delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
		177	enable_f0 : IN STD_LOGIC;
		178	enable_f1 : IN STD_LOGIC;
		179	enable_f2 : IN STD_LOGIC;
		180	enable_f3 : IN STD_LOGIC;
		181	burst_f0 : IN STD_LOGIC;
		182	burst_f1 : IN STD_LOGIC;
		183	burst_f2 : IN STD_LOGIC;
		184	nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
		185	nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
		186	status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		187	status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		188	status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		189	status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		190	addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		191	addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		192	addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		193	addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
		194	END COMPONENT;
		195
		196	COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
		197	GENERIC (
		198	hindex : INTEGER;
		199	nb_burst_available_size : INTEGER;
		200	nb_snapshot_param_size : INTEGER;
		201	delta_snapshot_size : INTEGER;
		202	delta_f2_f0_size : INTEGER;
		203	delta_f2_f1_size : INTEGER;
		204	tech : INTEGER);
		205	PORT (
		206	sample : IN Samples(7 DOWNTO 0);
		207	sample_val : IN STD_LOGIC;
156	cnv_clk : IN STD_LOGIC;	208	cnv_clk : IN STD_LOGIC;
157	cnv_rstn : IN STD_LOGIC;	209	cnv_rstn : IN STD_LOGIC;
158	clk : IN STD_LOGIC;	210	clk : IN STD_LOGIC;

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +223 -134

@@ -21,28 +21,29 USE GRLIB.DMA2AHB_Package.ALL;
21		21
22	ENTITY lpp_top_lfr_wf_picker IS	22	ENTITY lpp_top_lfr_wf_picker IS
23	GENERIC (	23	GENERIC (
24	hindex : INTEGER := 2;	24	hindex : INTEGER := 2;
25	pindex : INTEGER := 15;	25	pindex : INTEGER := 15;
26	paddr : INTEGER := 15;	26	paddr : INTEGER := 15;
27	pmask : INTEGER := 16#fff#;	27	pmask : INTEGER := 16#fff#;
28	pirq : INTEGER := 15;	28	pirq : INTEGER := 15;
29	tech : INTEGER := 0;	29	tech : INTEGER := 0;
30	nb_burst_available_size : INTEGER := 11;	30	nb_burst_available_size : INTEGER := 11;
31	nb_snapshot_param_size : INTEGER := 11;	31	nb_snapshot_param_size : INTEGER := 11;
32	delta_snapshot_size : INTEGER := 16;	32	delta_snapshot_size : INTEGER := 16;
33	delta_f2_f0_size : INTEGER := 10;	33	delta_f2_f0_size : INTEGER := 10;
34	delta_f2_f1_size : INTEGER := 10	34	delta_f2_f1_size : INTEGER := 10;
		35	ENABLE_FILTER : STD_LOGIC := '1'
35	);	36	);
36	PORT (	37	PORT (
37	-- ADS7886	38	-- ADS7886
38	cnv_run : IN STD_LOGIC;	39	cnv_run : IN STD_LOGIC;
39	cnv : OUT STD_LOGIC;	40	cnv : OUT STD_LOGIC;
40	sck : OUT STD_LOGIC;	41	sck : OUT STD_LOGIC;
41	sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);	42	sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
42	--	43	--
43	cnv_clk : IN STD_LOGIC;	44	cnv_clk : IN STD_LOGIC;
44	cnv_rstn : IN STD_LOGIC;	45	cnv_rstn : IN STD_LOGIC;
45		46
46	-- AMBA AHB system signals	47	-- AMBA AHB system signals
47	HCLK : IN STD_ULOGIC;	48	HCLK : IN STD_ULOGIC;
48	HRESETn : IN STD_ULOGIC;	49	HRESETn : IN STD_ULOGIC;
@@ -57,9 +58,9 ENTITY lpp_top_lfr_wf_picker IS
57		58
58	--	59	--
59	coarse_time_0 : IN STD_LOGIC;	60	coarse_time_0 : IN STD_LOGIC;
60		61
61	--	62	--
62	data_shaping_BW : OUT STD_LOGIC	63	data_shaping_BW : OUT STD_LOGIC
63	);	64	);
64	END lpp_top_lfr_wf_picker;	65	END lpp_top_lfr_wf_picker;
65		66
@@ -84,53 +85,58 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
84	SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	85	SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85	SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	86	SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86	SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	87	SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
88	SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
89	SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
90	SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91	SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92	SIGNAL data_shaping_SP0 : STD_LOGIC;
93	SIGNAL data_shaping_SP1 : STD_LOGIC;
94	SIGNAL data_shaping_R0 : STD_LOGIC;
95	SIGNAL data_shaping_R1 : STD_LOGIC;
96	SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
97	SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
98	SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
99	SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
100	SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
101	SIGNAL enable_f0 : STD_LOGIC;
102	SIGNAL enable_f1 : STD_LOGIC;
103	SIGNAL enable_f2 : STD_LOGIC;
104	SIGNAL enable_f3 : STD_LOGIC;
105	SIGNAL burst_f0 : STD_LOGIC;
106	SIGNAL burst_f1 : STD_LOGIC;
107	SIGNAL burst_f2 : STD_LOGIC;
108	SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109	SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110	SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111	SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112		88
113	SIGNAL s~~ample_f0_wen~~ : STD_LOGIC_VECTOR(5 DOWNTO 0);	89	SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
114	SIGNAL s~~ample_f0_wdata~~ : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	90	SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
115	SIGNAL s~~ample_f1_wen~~ : STD_LOGIC_VECTOR(5 DOWNTO 0);	91	SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
116	SIGNAL s~~ample_f1_wdata~~ : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	92	SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117	SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);	93	SIGNAL data_shaping_SP0 : STD_LOGIC;
118	SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	94	SIGNAL data_shaping_SP1 : STD_LOGIC;
119	SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);	95	SIGNAL data_shaping_R0 : STD_LOGIC;
120	SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);	96	SIGNAL data_shaping_R1 : STD_LOGIC;
121		97	SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
		98	SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
		99	SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
		100	SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
		101	SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
		102	SIGNAL enable_f0 : STD_LOGIC;
		103	SIGNAL enable_f1 : STD_LOGIC;
		104	SIGNAL enable_f2 : STD_LOGIC;
		105	SIGNAL enable_f3 : STD_LOGIC;
		106	SIGNAL burst_f0 : STD_LOGIC;
		107	SIGNAL burst_f1 : STD_LOGIC;
		108	SIGNAL burst_f2 : STD_LOGIC;
		109	SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
		110	SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
		111	SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
		112	SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
		113
		114	SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
		115	SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		116	SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
		117	SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		118	SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
		119	SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		120	SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
		121	SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		122
		123	CONSTANT ChanelCount : INTEGER := 8;
		124	CONSTANT ncycle_cnv_high : INTEGER := 40;
		125	CONSTANT ncycle_cnv : INTEGER := 250;
		126	SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
		127	SIGNAL sample_val : STD_LOGIC;
122		128
123	BEGIN	129	BEGIN
124		130
125	ready_matrix_f0_0 <= '0';	131	ready_matrix_f0_0 <= '0';
126	ready_matrix_f0_1 <= '0';	132	ready_matrix_f0_1 <= '0';
127	ready_matrix_f1 <= '0';	133	ready_matrix_f1 <= '0';
128	ready_matrix_f2 <= '0';	134	ready_matrix_f2 <= '0';
129	error_anticipating_empty_fifo <= '0';	135	error_anticipating_empty_fifo <= '0';
130	error_bad_component_error <= '0';	136	error_bad_component_error <= '0';
131	debug_reg <= (~~others~~ => '0');	137	debug_reg <= (OTHERS => '0');
132		138
133	lpp_top_apbreg_1: lpp_top_apbreg	139	lpp_top_apbreg_1 : lpp_top_apbreg
134	GENERIC MAP (	140	GENERIC MAP (
135	nb_burst_available_size => nb_burst_available_size,	141	nb_burst_available_size => nb_burst_available_size,
136	nb_snapshot_param_size => nb_snapshot_param_size,	142	nb_snapshot_param_size => nb_snapshot_param_size,
@@ -142,11 +148,11 BEGIN
142	pmask => pmask,	148	pmask => pmask,
143	pirq => pirq)	149	pirq => pirq)
144	PORT MAP (	150	PORT MAP (
145	HCLK => HCLK,	151	HCLK => HCLK,
146	HRESETn => HRESETn,	152	HRESETn => HRESETn,
147	apbi => apbi,	153	apbi => apbi,
148	apbo => apbo,	154	apbo => apbo,
149		155
150	ready_matrix_f0_0 => ready_matrix_f0_0,	156	ready_matrix_f0_0 => ready_matrix_f0_0,
151	ready_matrix_f0_1 => ready_matrix_f0_1,	157	ready_matrix_f0_1 => ready_matrix_f0_1,
152	ready_matrix_f1 => ready_matrix_f1,	158	ready_matrix_f1 => ready_matrix_f1,
@@ -166,66 +172,12 BEGIN
166	addr_matrix_f0_1 => addr_matrix_f0_1,	172	addr_matrix_f0_1 => addr_matrix_f0_1,
167	addr_matrix_f1 => addr_matrix_f1,	173	addr_matrix_f1 => addr_matrix_f1,
168	addr_matrix_f2 => addr_matrix_f2,	174	addr_matrix_f2 => addr_matrix_f2,
169
170	status_full => status_full,
171	status_full_ack => status_full_ack,
172	status_full_err => status_full_err,
173	status_new_err => status_new_err,
174	data_shaping_BW => data_shaping_BW,
175	data_shaping_SP0 => data_shaping_SP0,
176	data_shaping_SP1 => data_shaping_SP1,
177	data_shaping_R0 => data_shaping_R0,
178	data_shaping_R1 => data_shaping_R1,
179	delta_snapshot => delta_snapshot,
180	delta_f2_f1 => delta_f2_f1,
181	delta_f2_f0 => delta_f2_f0,
182	nb_burst_available => nb_burst_available,
183	nb_snapshot_param => nb_snapshot_param,
184	enable_f0 => enable_f0,
185	enable_f1 => enable_f1,
186	enable_f2 => enable_f2,
187	enable_f3 => enable_f3,
188	burst_f0 => burst_f0,
189	burst_f1 => burst_f1,
190	burst_f2 => burst_f2,
191	addr_data_f0 => addr_data_f0,
192	addr_data_f1 => addr_data_f1,
193	addr_data_f2 => addr_data_f2,
194	addr_data_f3 => addr_data_f3);
195		175
196	lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip	176	status_full => status_full,
197	GENERIC MAP (	177	status_full_ack => status_full_ack,
198	hindex => hindex,	178	status_full_err => status_full_err,
199	nb_burst_available_size => nb_burst_available_size,	179	status_new_err => status_new_err,
200	nb_snapshot_param_size => nb_snapshot_param_size,	180	data_shaping_BW => data_shaping_BW,
201	delta_snapshot_size => delta_snapshot_size,
202	delta_f2_f0_size => delta_f2_f0_size,
203	delta_f2_f1_size => delta_f2_f1_size,
204	tech => tech,
205	Mem_use => use_RAM
206	)
207	PORT MAP (
208	cnv_run => cnv_run,
209	cnv => cnv,
210	sck => sck,
211	sdo => sdo,
212	cnv_clk => cnv_clk,
213	cnv_rstn => cnv_rstn,
214
215	clk => HCLK,
216	rstn => HRESETn,
217
218	sample_f0_wen => sample_f0_wen,
219	sample_f0_wdata => sample_f0_wdata,
220	sample_f1_wen => sample_f1_wen,
221	sample_f1_wdata => sample_f1_wdata,
222	sample_f2_wen => sample_f2_wen,
223	sample_f2_wdata => sample_f2_wdata,
224	sample_f3_wen => sample_f3_wen,
225	sample_f3_wdata => sample_f3_wdata,
226	AHB_Master_In => AHB_Master_In,
227	AHB_Master_Out => AHB_Master_Out,
228	coarse_time_0 => coarse_time_0,
229	data_shaping_SP0 => data_shaping_SP0,	181	data_shaping_SP0 => data_shaping_SP0,
230	data_shaping_SP1 => data_shaping_SP1,	182	data_shaping_SP1 => data_shaping_SP1,
231	data_shaping_R0 => data_shaping_R0,	183	data_shaping_R0 => data_shaping_R0,
@@ -233,6 +185,8 BEGIN
233	delta_snapshot => delta_snapshot,	185	delta_snapshot => delta_snapshot,
234	delta_f2_f1 => delta_f2_f1,	186	delta_f2_f1 => delta_f2_f1,
235	delta_f2_f0 => delta_f2_f0,	187	delta_f2_f0 => delta_f2_f0,
		188	nb_burst_available => nb_burst_available,
		189	nb_snapshot_param => nb_snapshot_param,
236	enable_f0 => enable_f0,	190	enable_f0 => enable_f0,
237	enable_f1 => enable_f1,	191	enable_f1 => enable_f1,
238	enable_f2 => enable_f2,	192	enable_f2 => enable_f2,
@@ -240,14 +194,149 BEGIN
240	burst_f0 => burst_f0,	194	burst_f0 => burst_f0,
241	burst_f1 => burst_f1,	195	burst_f1 => burst_f1,
242	burst_f2 => burst_f2,	196	burst_f2 => burst_f2,
243	nb_burst_available => nb_burst_available,
244	nb_snapshot_param => nb_snapshot_param,
245	status_full => status_full,
246	status_full_ack => status_full_ack,
247	status_full_err => status_full_err,
248	status_new_err => status_new_err,
249	addr_data_f0 => addr_data_f0,	197	addr_data_f0 => addr_data_f0,
250	addr_data_f1 => addr_data_f1,	198	addr_data_f1 => addr_data_f1,
251	addr_data_f2 => addr_data_f2,	199	addr_data_f2 => addr_data_f2,
252	addr_data_f3 => addr_data_f3);	200	addr_data_f3 => addr_data_f3);
253	END tb; No newline at end of file	201
		202
		203
		204
		205	DIGITAL_acquisition : AD7688_drvr_sync
		206	GENERIC MAP (
		207	ChanelCount => ChanelCount,
		208	ncycle_cnv_high => ncycle_cnv_high,
		209	ncycle_cnv => ncycle_cnv)
		210	PORT MAP (
		211	cnv_clk => cnv_clk, --
		212	cnv_rstn => cnv_rstn, --
		213	cnv_run => cnv_run, --
		214	cnv => cnv, --
		215	sck => sck, --
		216	sdo => sdo(ChanelCount-1 DOWNTO 0), --
		217	sample => sample,
		218	sample_val => sample_val);
		219
		220
		221	wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
		222
		223	lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
		224	GENERIC MAP (
		225	hindex => hindex,
		226	nb_burst_available_size => nb_burst_available_size,
		227	nb_snapshot_param_size => nb_snapshot_param_size,
		228	delta_snapshot_size => delta_snapshot_size,
		229	delta_f2_f0_size => delta_f2_f0_size,
		230	delta_f2_f1_size => delta_f2_f1_size,
		231	tech => tech,
		232	Mem_use => use_RAM
		233	)
		234	PORT MAP (
		235	sample => sample,
		236	sample_val => sample_val,
		237
		238	cnv_clk => cnv_clk,
		239	cnv_rstn => cnv_rstn,
		240
		241	clk => HCLK,
		242	rstn => HRESETn,
		243
		244	sample_f0_wen => sample_f0_wen,
		245	sample_f0_wdata => sample_f0_wdata,
		246	sample_f1_wen => sample_f1_wen,
		247	sample_f1_wdata => sample_f1_wdata,
		248	sample_f2_wen => sample_f2_wen,
		249	sample_f2_wdata => sample_f2_wdata,
		250	sample_f3_wen => sample_f3_wen,
		251	sample_f3_wdata => sample_f3_wdata,
		252	AHB_Master_In => AHB_Master_In,
		253	AHB_Master_Out => AHB_Master_Out,
		254	coarse_time_0 => coarse_time_0,
		255	data_shaping_SP0 => data_shaping_SP0,
		256	data_shaping_SP1 => data_shaping_SP1,
		257	data_shaping_R0 => data_shaping_R0,
		258	data_shaping_R1 => data_shaping_R1,
		259	delta_snapshot => delta_snapshot,
		260	delta_f2_f1 => delta_f2_f1,
		261	delta_f2_f0 => delta_f2_f0,
		262	enable_f0 => enable_f0,
		263	enable_f1 => enable_f1,
		264	enable_f2 => enable_f2,
		265	enable_f3 => enable_f3,
		266	burst_f0 => burst_f0,
		267	burst_f1 => burst_f1,
		268	burst_f2 => burst_f2,
		269	nb_burst_available => nb_burst_available,
		270	nb_snapshot_param => nb_snapshot_param,
		271	status_full => status_full,
		272	status_full_ack => status_full_ack,
		273	status_full_err => status_full_err,
		274	status_new_err => status_new_err,
		275	addr_data_f0 => addr_data_f0,
		276	addr_data_f1 => addr_data_f1,
		277	addr_data_f2 => addr_data_f2,
		278	addr_data_f3 => addr_data_f3);
		279
		280	END GENERATE wf_picker_with_filter;
		281
		282
		283	wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
		284
		285	lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
		286	GENERIC MAP (
		287	hindex => hindex,
		288	nb_burst_available_size => nb_burst_available_size,
		289	nb_snapshot_param_size => nb_snapshot_param_size,
		290	delta_snapshot_size => delta_snapshot_size,
		291	delta_f2_f0_size => delta_f2_f0_size,
		292	delta_f2_f1_size => delta_f2_f1_size,
		293	tech => tech
		294	)
		295	PORT MAP (
		296	sample => sample,
		297	sample_val => sample_val,
		298
		299	cnv_clk => cnv_clk,
		300	cnv_rstn => cnv_rstn,
		301
		302	clk => HCLK,
		303	rstn => HRESETn,
		304
		305	sample_f0_wen => sample_f0_wen,
		306	sample_f0_wdata => sample_f0_wdata,
		307	sample_f1_wen => sample_f1_wen,
		308	sample_f1_wdata => sample_f1_wdata,
		309	sample_f2_wen => sample_f2_wen,
		310	sample_f2_wdata => sample_f2_wdata,
		311	sample_f3_wen => sample_f3_wen,
		312	sample_f3_wdata => sample_f3_wdata,
		313	AHB_Master_In => AHB_Master_In,
		314	AHB_Master_Out => AHB_Master_Out,
		315	coarse_time_0 => coarse_time_0,
		316	data_shaping_SP0 => data_shaping_SP0,
		317	data_shaping_SP1 => data_shaping_SP1,
		318	data_shaping_R0 => data_shaping_R0,
		319	data_shaping_R1 => data_shaping_R1,
		320	delta_snapshot => delta_snapshot,
		321	delta_f2_f1 => delta_f2_f1,
		322	delta_f2_f0 => delta_f2_f0,
		323	enable_f0 => enable_f0,
		324	enable_f1 => enable_f1,
		325	enable_f2 => enable_f2,
		326	enable_f3 => enable_f3,
		327	burst_f0 => burst_f0,
		328	burst_f1 => burst_f1,
		329	burst_f2 => burst_f2,
		330	nb_burst_available => nb_burst_available,
		331	nb_snapshot_param => nb_snapshot_param,
		332	status_full => status_full,
		333	status_full_ack => status_full_ack,
		334	status_full_err => status_full_err,
		335	status_new_err => status_new_err,
		336	addr_data_f0 => addr_data_f0,
		337	addr_data_f1 => addr_data_f1,
		338	addr_data_f2 => addr_data_f2,
		339	addr_data_f3 => addr_data_f3);
		340
		341	END GENERATE wf_picker_without_filter;
		342	END tb;

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +227 -145

@@ -8,6 +8,7 USE lpp.iir_filter.ALL;
8	USE lpp.FILTERcfg.ALL;	8	USE lpp.FILTERcfg.ALL;
9	USE lpp.lpp_memory.ALL;	9	USE lpp.lpp_memory.ALL;
10	USE lpp.lpp_waveform_pkg.ALL;	10	USE lpp.lpp_waveform_pkg.ALL;
		11	USE lpp.general_purpose.SYNC_FF;
11		12
12	LIBRARY techmap;	13	LIBRARY techmap;
13	USE techmap.gencomp.ALL;	14	USE techmap.gencomp.ALL;
@@ -20,21 +21,23 USE GRLIB.DMA2AHB_Package.ALL;
20		21
21	ENTITY lpp_top_lfr_wf_picker_ip IS	22	ENTITY lpp_top_lfr_wf_picker_ip IS
22	GENERIC(	23	GENERIC(
23	hindex : INTEGER := 2;	24	hindex : INTEGER := 2;
24	nb_burst_available_size : INTEGER := 11;	25	nb_burst_available_size : INTEGER := 11;
25	nb_snapshot_param_size : INTEGER := 11;	26	nb_snapshot_param_size : INTEGER := 11;
26	delta_snapshot_size : INTEGER := 16;	27	delta_snapshot_size : INTEGER := 16;
27	delta_f2_f0_size : INTEGER := 10;	28	delta_f2_f0_size : INTEGER := 10;
28	delta_f2_f1_size : INTEGER := 10;	29	delta_f2_f1_size : INTEGER := 10;
29	tech : INTEGER := 0;	30	tech : INTEGER := 0;
30	Mem_use : INTEGER := use_RAM	31	Mem_use : INTEGER := use_RAM
31	);	32	);
32	PORT (	33	PORT (
33	-- ADS7886	34	-- ADS7886
34	cnv_run : IN STD_LOGIC;	35	-- cnv_run : IN STD_LOGIC;
35	cnv : OUT STD_LOGIC;	36	-- cnv : OUT STD_LOGIC;
36	sck : OUT STD_LOGIC;	37	-- sck : OUT STD_LOGIC;
37	sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);	38	-- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		39	sample : IN Samples(7 DOWNTO 0);
		40	sample_val : IN STD_LOGIC;
38	--	41	--
39	cnv_clk : IN STD_LOGIC;	42	cnv_clk : IN STD_LOGIC;
40	cnv_rstn : IN STD_LOGIC;	43	cnv_rstn : IN STD_LOGIC;
@@ -61,11 +64,11 ENTITY lpp_top_lfr_wf_picker_ip IS
61	coarse_time_0 : IN STD_LOGIC;	64	coarse_time_0 : IN STD_LOGIC;
62		65
63	--config	66	--config
64	data_shaping_SP0 : IN STD_LOGIC;	67	data_shaping_SP0 : IN STD_LOGIC;
65	data_shaping_SP1 : IN STD_LOGIC;	68	data_shaping_SP1 : IN STD_LOGIC;
66	data_shaping_R0 : IN STD_LOGIC;	69	data_shaping_R0 : IN STD_LOGIC;
67	data_shaping_R1 : IN STD_LOGIC;	70	data_shaping_R1 : IN STD_LOGIC;
68		71
69	delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);	72	delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
70	delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);	73	delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
71	delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);	74	delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
@@ -80,11 +83,11 ENTITY lpp_top_lfr_wf_picker_ip IS
80	burst_f2 : IN STD_LOGIC;	83	burst_f2 : IN STD_LOGIC;
81		84
82	nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);	85	nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
83	nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	86	nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
84	status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	87	status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
85	status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	88	status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86	status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	89	status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
87	status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma	90	status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
88		91
89	addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	92	addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90	addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	93	addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -109,14 +112,20 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
109	sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));	112	sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
110	END COMPONENT;	113	END COMPONENT;
111		114
		115	COMPONENT SYNC_FF
		116	GENERIC (
		117	NB_FF_OF_SYNC : INTEGER);
		118	PORT (
		119	clk : IN STD_LOGIC;
		120	rstn : IN STD_LOGIC;
		121	A : IN STD_LOGIC;
		122	A_sync : OUT STD_LOGIC);
		123	END COMPONENT;
		124
112	-----------------------------------------------------------------------------	125	-----------------------------------------------------------------------------
113	CONSTANT ChanelCount : INTEGER := 8;	126	CONSTANT ChanelCount : INTEGER := 8;
114	CONSTANT ncycle_cnv_high : INTEGER := 79;
115	CONSTANT ncycle_cnv : INTEGER := 500;
116		127
117	-----------------------------------------------------------------------------	128	-----------------------------------------------------------------------------
118	SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
119	SIGNAL sample_val : STD_LOGIC;
120	SIGNAL sample_val_delay : STD_LOGIC;	129	SIGNAL sample_val_delay : STD_LOGIC;
121	-----------------------------------------------------------------------------	130	-----------------------------------------------------------------------------
122	CONSTANT Coef_SZ : INTEGER := 9;	131	CONSTANT Coef_SZ : INTEGER := 9;
@@ -132,30 +141,40 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
132	SIGNAL sample_filter_v2_out_val : STD_LOGIC;	141	SIGNAL sample_filter_v2_out_val : STD_LOGIC;
133	SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);	142	SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
134	-----------------------------------------------------------------------------	143	-----------------------------------------------------------------------------
135	SIGNAL sample_data_shaping_out_val : STD_LOGIC;	144	SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136	SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);	145
137	SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);	146	SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
138	SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);	147	SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
139	SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);	148	SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
140	SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);	149	SIGNAL only_one_hot : STD_LOGIC;
141	SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);	150	SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
142	-----------------------------------------------------------------------------	151	SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
143	SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;	152	SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
144	SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
145	-----------------------------------------------------------------------------	153	-----------------------------------------------------------------------------
146	SIGNAL sample_f0_val : STD_LOGIC;	154	SIGNAL sample_data_shaping_out_val : STD_LOGIC;
147	SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);	155	SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
148	SIGNAL sample_f0_s : ~~samplT~~(5 ~~DOWNTO~~ 0, 15 DOWNTO 0);	156	SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
		157	SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
		158	SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
		159	SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
		160	SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
		161	-----------------------------------------------------------------------------
		162	SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
		163	SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
		164	-----------------------------------------------------------------------------
		165	SIGNAL sample_f0_val : STD_LOGIC;
		166	SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
		167	SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
149	--	168	--
150	SIGNAL sample_f1_val : STD_LOGIC;	169	SIGNAL sample_f1_val : STD_LOGIC;
151	SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);	170	SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
152	SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);	171	SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
153	--	172	--
154	SIGNAL sample_f2_val : STD_LOGIC;	173	SIGNAL sample_f2_val : STD_LOGIC;
155	SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);	174	SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
156	--	175	--
157	SIGNAL sample_f3_val : STD_LOGIC;	176	SIGNAL sample_f3_val : STD_LOGIC;
158	SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);	177	SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
159		178
160	-----------------------------------------------------------------------------	179	-----------------------------------------------------------------------------
161	SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');	180	SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
@@ -163,39 +182,19 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
163	SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');	182	SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
164	SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');	183	SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
165	-----------------------------------------------------------------------------	184	-----------------------------------------------------------------------------
		185
		186	SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		187	SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		188	SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		189	SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
		190	BEGIN
166		191
167	SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168	SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
169	SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
170	SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
171	BEGIN
172
173	-- component instantiation
174	-----------------------------------------------------------------------------	192	-----------------------------------------------------------------------------
175	DIGITAL_acquisition : AD7688_drvr	193	PROCESS (cnv_clk, cnv_rstn)
176	GENERIC MAP (
177	ChanelCount => ChanelCount,
178	ncycle_cnv_high => ncycle_cnv_high,
179	ncycle_cnv => ncycle_cnv)
180	PORT MAP (
181	cnv_clk => cnv_clk, --
182	cnv_rstn => cnv_rstn, --
183	cnv_run => cnv_run, --
184	cnv => cnv, --
185	clk => clk, --
186	rstn => rstn, --
187	sck => sck, --
188	sdo => sdo(ChanelCount-1 DOWNTO 0), --
189	sample => sample,
190	sample_val => sample_val);
191
192	-----------------------------------------------------------------------------
193
194	PROCESS (clk, rstn)
195	BEGIN -- PROCESS	194	BEGIN -- PROCESS
196	IF rstn = '0' THEN -- asynchronous reset (active low)	195	IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
197	sample_val_delay <= '0';	196	sample_val_delay <= '0';
198	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	197	ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
199	sample_val_delay <= sample_val;	198	sample_val_delay <= sample_val;
200	END IF;	199	END IF;
201	END PROCESS;	200	END PROCESS;
@@ -223,8 +222,8 BEGIN
223	Cels_count => Cels_count,	222	Cels_count => Cels_count,
224	ChanelsCount => ChanelCount)	223	ChanelsCount => ChanelCount)
225	PORT MAP (	224	PORT MAP (
226	rstn => rstn,	225	rstn => cnv_rstn,
227	clk => clk,	226	clk => cnv_clk,
228	virg_pos => 7,	227	virg_pos => 7,
229	coefs => coefs_v2,	228	coefs => coefs_v2,
230	sample_in_val => sample_val_delay,	229	sample_in_val => sample_val_delay,
@@ -232,15 +231,97 BEGIN
232	sample_out_val => sample_filter_v2_out_val,	231	sample_out_val => sample_filter_v2_out_val,
233	sample_out => sample_filter_v2_out);	232	sample_out => sample_filter_v2_out);
234		233
		234
		235	-----------------------------------------------------------------------------
		236	-- RESYNC STAGE
		237	-----------------------------------------------------------------------------
		238
		239	all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
		240	all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
		241	PROCESS (cnv_clk, cnv_rstn)
		242	BEGIN -- PROCESS
		243	IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
		244	sample_filter_v2_out_reg(I, J) <= '0';
		245	ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
		246	IF sample_filter_v2_out_val = '1' THEN
		247	sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
		248	END IF;
		249	END IF;
		250	END PROCESS;
		251	END GENERATE all_data_reg;
		252	END GENERATE all_sample_reg;
		253
		254	PROCESS (cnv_clk, cnv_rstn)
		255	BEGIN -- PROCESS
		256	IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
		257	sample_filter_v2_out_reg_val <= '0';
		258	ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
		259	IF sample_filter_v2_out_val = '1' THEN
		260	sample_filter_v2_out_reg_val <= '1';
		261	ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
		262	sample_filter_v2_out_reg_val <= '0';
		263	END IF;
		264	END IF;
		265	END PROCESS;
		266
		267	SYNC_FF_1 : SYNC_FF
		268	GENERIC MAP (
		269	NB_FF_OF_SYNC => 2)
		270	PORT MAP (
		271	clk => clk,
		272	rstn => rstn,
		273	A => sample_filter_v2_out_reg_val,
		274	A_sync => sample_filter_v2_out_reg_val_s);
		275
		276	SYNC_FF_2 : SYNC_FF
		277	GENERIC MAP (
		278	NB_FF_OF_SYNC => 2)
		279	PORT MAP (
		280	clk => cnv_clk,
		281	rstn => cnv_rstn,
		282	A => sample_filter_v2_out_reg_val_s,
		283	A_sync => sample_filter_v2_out_reg_val_s2);
		284
		285
		286	PROCESS (clk, rstn)
		287	BEGIN -- PROCESS
		288	IF rstn = '0' THEN -- asynchronous reset (active low)
		289	sample_filter_v2_out_sync_val_t <= '0';
		290	sample_filter_v2_out_sync_val <= '0';
		291	only_one_hot <= '0';
		292	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
		293	sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
		294	only_one_hot <= sample_filter_v2_out_reg_val_s;
		295	sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
		296	END IF;
		297	END PROCESS;
		298
		299
		300	all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
		301	all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
		302	PROCESS (clk, cnv_rstn)
		303	BEGIN -- PROCESS
		304	IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
		305	sample_filter_v2_out_sync(I,J) <= '0';
		306	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
		307	IF sample_filter_v2_out_sync_val_t = '1' THEN
		308	sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
		309	END IF;
		310	END IF;
		311	END PROCESS;
		312	END GENERATE all_data_reg;
		313	END GENERATE all_sample_reg2;
		314
		315
235	-----------------------------------------------------------------------------	316	-----------------------------------------------------------------------------
236	-- DATA_SHAPING	317	-- DATA_SHAPING
237	-----------------------------------------------------------------------------	318	-----------------------------------------------------------------------------
238	all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE	319	all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
239	sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);	320	sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
240	sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);	321	sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
241	sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);	322	sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
242	END GENERATE all_data_shaping_in_loop;	323	END GENERATE all_data_shaping_in_loop;
243		324
244	sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;	325	sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
245	sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;	326	sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
246		327
@@ -248,47 +329,48 BEGIN
248	BEGIN -- PROCESS	329	BEGIN -- PROCESS
249	IF rstn = '0' THEN -- asynchronous reset (active low)	330	IF rstn = '0' THEN -- asynchronous reset (active low)
250	sample_data_shaping_out_val <= '0';	331	sample_data_shaping_out_val <= '0';
251	ELSIF clk'~~event~~ AND clk = '1' THEN -- rising clock edge	332	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
252	sample_data_shaping_out_val <= sample_filter_v2_out_val;	333	sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
253	END IF;	334	END IF;
254	END PROCESS;	335	END PROCESS;
255		336
256	SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE	337	SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
257	PROCESS (clk, rstn)	338	PROCESS (clk, rstn)
258	BEGIN	339	BEGIN
259	IF rstn = '0' THEN	340	IF rstn = '0' THEN
260	sample_data_shaping_out(0,j) <= '0';	341	sample_data_shaping_out(0, j) <= '0';
261	sample_data_shaping_out(1,j) <= '0';	342	sample_data_shaping_out(1, j) <= '0';
262	sample_data_shaping_out(2,j) <= '0';	343	sample_data_shaping_out(2, j) <= '0';
263	sample_data_shaping_out(3,j) <= '0';	344	sample_data_shaping_out(3, j) <= '0';
264	sample_data_shaping_out(4,j) <= '0';	345	sample_data_shaping_out(4, j) <= '0';
265	sample_data_shaping_out(5,j) <= '0';	346	sample_data_shaping_out(5, j) <= '0';
266	sample_data_shaping_out(6,j) <= '0';	347	sample_data_shaping_out(6, j) <= '0';
267	sample_data_shaping_out(7,j) <= '0';	348	sample_data_shaping_out(7, j) <= '0';
268	ELSIF clk'~~event~~ AND clk = '1' THEN -- rising clock edge	349	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
269	sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);	350	sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
270	IF data_shaping_SP0 = '1' THEN	351	IF data_shaping_SP0 = '1' THEN
271	sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);	352	sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
272	ELSE	353	ELSE
273	sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);	354	sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
274	END IF;	355	END IF;
275	IF data_shaping_SP1 = '1' THEN	356	IF data_shaping_SP1 = '1' THEN
276	sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);	357	sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
277	ELSE	358	ELSE
278	sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);	359	sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
279	END IF;	360	END IF;
280	sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);	361	sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
281	sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);	362	sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
282	sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);	363	sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
283	sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);	364	sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
		365	sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
284	END IF;	366	END IF;
285	END PROCESS;	367	END PROCESS;
286	END GENERATE;	368	END GENERATE;
287		369
288	sample_filter_v2_out_val_s <= sample_data_shaping_out_val;	370	sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
289	ChanelLoopOut : FOR i IN 0 TO 7 GENERATE	371	ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
290	SampleLoopOut : FOR j IN 0 TO 15 GENERATE	372	SampleLoopOut : FOR j IN 0 TO 15 GENERATE
291	sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);	373	sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
292	END GENERATE;	374	END GENERATE;
293	END GENERATE;	375	END GENERATE;
294	-----------------------------------------------------------------------------	376	-----------------------------------------------------------------------------
@@ -306,7 +388,7 BEGIN
306	sample_in => sample_filter_v2_out_s,	388	sample_in => sample_filter_v2_out_s,
307	sample_out_val => sample_f0_val,	389	sample_out_val => sample_f0_val,
308	sample_out => sample_f0);	390	sample_out => sample_f0);
309		391
310	all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE	392	all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
311	sample_f0_wdata_s(I) <= sample_f0(0, I); -- V	393	sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
312	sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1	394	sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
@@ -338,16 +420,16 BEGIN
338	sample_in => sample_f0,	420	sample_in => sample_f0,
339	sample_out_val => sample_f1_val,	421	sample_out_val => sample_f1_val,
340	sample_out => sample_f1);	422	sample_out => sample_f1);
341		423
342	all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE	424	all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
343	sample_f1_wdata_s(I) <= sample_f1(0, I); -- V	425	sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
344	sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1	426	sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
345	sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2	427	sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
346	sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1	428	sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
347	sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2	429	sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
348	sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3	430	sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
349	END GENERATE all_bit_sample_f1;	431	END GENERATE all_bit_sample_f1;
350		432
351	sample_f1_wen <= NOT(sample_f1_val) &	433	sample_f1_wen <= NOT(sample_f1_val) &
352	NOT(sample_f1_val) &	434	NOT(sample_f1_val) &
353	NOT(sample_f1_val) &	435	NOT(sample_f1_val) &
@@ -366,7 +448,7 BEGIN
366	sample_f0_s(4, I) <= sample_f0(6, I); -- B2	448	sample_f0_s(4, I) <= sample_f0(6, I); -- B2
367	sample_f0_s(5, I) <= sample_f0(7, I); -- B3	449	sample_f0_s(5, I) <= sample_f0(7, I); -- B3
368	END GENERATE all_bit_sample_f0_s;	450	END GENERATE all_bit_sample_f0_s;
369		451
370	Downsampling_f2 : Downsampling	452	Downsampling_f2 : Downsampling
371	GENERIC MAP (	453	GENERIC MAP (
372	ChanelCount => 6,	454	ChanelCount => 6,
@@ -407,7 +489,7 BEGIN
407	sample_f1_s(4, I) <= sample_f1(6, I); -- B2	489	sample_f1_s(4, I) <= sample_f1(6, I); -- B2
408	sample_f1_s(5, I) <= sample_f1(7, I); -- B3	490	sample_f1_s(5, I) <= sample_f1(7, I); -- B3
409	END GENERATE all_bit_sample_f1_s;	491	END GENERATE all_bit_sample_f1_s;
410		492
411	Downsampling_f3 : Downsampling	493	Downsampling_f3 : Downsampling
412	GENERIC MAP (	494	GENERIC MAP (
413	ChanelCount => 6,	495	ChanelCount => 6,
@@ -439,14 +521,14 BEGIN
439		521
440	lpp_waveform_1 : lpp_waveform	522	lpp_waveform_1 : lpp_waveform
441	GENERIC MAP (	523	GENERIC MAP (
442	hindex => hindex,	524	hindex => hindex,
443	tech => tech,	525	tech => tech,
444	data_size => 160,	526	data_size => 160,
445	nb_burst_available_size => nb_burst_available_size,	527	nb_burst_available_size => nb_burst_available_size,
446	nb_snapshot_param_size => nb_snapshot_param_size,	528	nb_snapshot_param_size => nb_snapshot_param_size,
447	delta_snapshot_size => delta_snapshot_size,	529	delta_snapshot_size => delta_snapshot_size,
448	delta_f2_f0_size => delta_f2_f0_size,	530	delta_f2_f0_size => delta_f2_f0_size,
449	delta_f2_f1_size => delta_f2_f1_size)	531	delta_f2_f1_size => delta_f2_f1_size)
450	PORT MAP (	532	PORT MAP (
451	clk => clk,	533	clk => clk,
452	rstn => rstn,	534	rstn => rstn,
@@ -454,44 +536,44 BEGIN
454	AHB_Master_In => AHB_Master_In,	536	AHB_Master_In => AHB_Master_In,
455	AHB_Master_Out => AHB_Master_Out,	537	AHB_Master_Out => AHB_Master_Out,
456		538
457	coarse_time_0 => coarse_time_0, -- IN	539	coarse_time_0 => coarse_time_0, -- IN
458	delta_snapshot => delta_snapshot, -- IN	540	delta_snapshot => delta_snapshot, -- IN
459	delta_f2_f1 => delta_f2_f1, -- IN	541	delta_f2_f1 => delta_f2_f1, -- IN
460	delta_f2_f0 => delta_f2_f0, -- IN	542	delta_f2_f0 => delta_f2_f0, -- IN
461	enable_f0 => enable_f0, -- IN	543	enable_f0 => enable_f0, -- IN
462	enable_f1 => enable_f1, -- IN	544	enable_f1 => enable_f1, -- IN
463	enable_f2 => enable_f2, -- IN	545	enable_f2 => enable_f2, -- IN
464	enable_f3 => enable_f3, -- IN	546	enable_f3 => enable_f3, -- IN
465	burst_f0 => burst_f0, -- IN	547	burst_f0 => burst_f0, -- IN
466	burst_f1 => burst_f1, -- IN	548	burst_f1 => burst_f1, -- IN
467	burst_f2 => burst_f2, -- IN	549	burst_f2 => burst_f2, -- IN
468	nb_burst_available => nb_burst_available,	550	nb_burst_available => nb_burst_available,
469	nb_snapshot_param => nb_snapshot_param,	551	nb_snapshot_param => nb_snapshot_param,
470	status_full => status_full,	552	status_full => status_full,
471	status_full_ack => status_full_ack, -- IN	553	status_full_ack => status_full_ack, -- IN
472	status_full_err => status_full_err,	554	status_full_err => status_full_err,
473	status_new_err => status_new_err,	555	status_new_err => status_new_err,
474		556
475	addr_data_f0 => addr_data_f0, -- IN	557	addr_data_f0 => addr_data_f0, -- IN
476	addr_data_f1 => addr_data_f1, -- IN	558	addr_data_f1 => addr_data_f1, -- IN
477	addr_data_f2 => addr_data_f2, -- IN	559	addr_data_f2 => addr_data_f2, -- IN
478	addr_data_f3 => addr_data_f3, -- IN	560	addr_data_f3 => addr_data_f3, -- IN
479		561
480	data_f0_in => data_f0_in_valid,	562	data_f0_in => data_f0_in_valid,
481	data_f1_in => data_f1_in_valid,	563	data_f1_in => data_f1_in_valid,
482	data_f2_in => data_f2_in_valid,	564	data_f2_in => data_f2_in_valid,
483	data_f3_in => data_f3_in_valid,	565	data_f3_in => data_f3_in_valid,
484		566
485	data_f0_in_valid => sample_f0_val,	567	data_f0_in_valid => sample_f0_val,
486	data_f1_in_valid => sample_f1_val,	568	data_f1_in_valid => sample_f1_val,
487	data_f2_in_valid => sample_f2_val,	569	data_f2_in_valid => sample_f2_val,
488	data_f3_in_valid => sample_f3_val);	570	data_f3_in_valid => sample_f3_val);
489		571
490	data_f0_in_valid((4*16)-1 DOWNTO 0) <= (~~others~~ => '0');	572	data_f0_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
491	data_f1_in_valid((4*16)-1 DOWNTO 0) <= (~~others~~ => '0');	573	data_f1_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
492	data_f2_in_valid((4*16)-1 DOWNTO 0) <= (~~others~~ => '0');	574	data_f2_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
493	data_f3_in_valid((4*16)-1 DOWNTO 0) <= (~~others~~ => '0');	575	data_f3_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
494		576
495	data_f0_in_valid((1016)-1 DOWNTO (416)) <= sample_f0_wdata_s;	577	data_f0_in_valid((1016)-1 DOWNTO (416)) <= sample_f0_wdata_s;
496	data_f1_in_valid((1016)-1 DOWNTO (416)) <= sample_f1_wdata_s;	578	data_f1_in_valid((1016)-1 DOWNTO (416)) <= sample_f1_wdata_s;
497	data_f2_in_valid((1016)-1 DOWNTO (416)) <= sample_f2_wdata_s;	579	data_f2_in_valid((1016)-1 DOWNTO (416)) <= sample_f2_wdata_s;

lib/lpp/lpp_top_lfr/vhdlsyn.txt +1 0

             lpp_top_apbreg.vhd
             lpp_top_lfr_wf_picker.vhd
             lpp_top_lfr_wf_picker_ip.vhd
+            lpp_top_lfr_wf_picker_ip_whitout_filter.vhd

lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +1 0

                   send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
                   send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
+                  count_send_time <= 0;
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN
                   CASE state IS

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages