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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.stdlib.ALL;
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LIBRARY gaisler;
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USE gaisler.libdcom.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.jtagtst.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.lpp_sim_pkg.ALL;
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USE lpp.lpp_lfr_apbreg_pkg.ALL;
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USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
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PACKAGE lpp_lfr_sim_pkg IS
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PROCEDURE UNRESET_LFR (
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SIGNAL TX : OUT STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
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);
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PROCEDURE LAUNCH_SPECTRAL_MATRIX(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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-----------------------------------------------------------------------------
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-- SM function
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-----------------------------------------------------------------------------
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PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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PROCEDURE SET_SM_IRQ_onNewMatrix(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_value : IN STD_LOGIC
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);
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PROCEDURE SET_SM_IRQ_ERROR(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_value : IN STD_LOGIC
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);
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PROCEDURE RESET_SM_STATUS(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
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);
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END lpp_lfr_sim_pkg;
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PACKAGE BODY lpp_lfr_sim_pkg IS
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PROCEDURE UNRESET_LFR (
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SIGNAL TX : OUT STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
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IS
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BEGIN
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UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
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UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
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END;
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PROCEDURE LAUNCH_SPECTRAL_MATRIX(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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)
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IS
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BEGIN
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RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
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PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
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PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
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SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
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'1');
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END;
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-----------------------------------------------------------------------------
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-- SM function
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-----------------------------------------------------------------------------
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PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
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CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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)
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IS
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BEGIN
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SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
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SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
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RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
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UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
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END;
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PROCEDURE SET_SM_IRQ_onNewMatrix(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
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CONSTANT PARAM_value : IN STD_LOGIC
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)
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IS
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VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
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IF PARAM_value = '1' THEN
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UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
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ELSE
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UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
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END IF;
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END;
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PROCEDURE SET_SM_IRQ_ERROR(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
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CONSTANT PARAM_value : IN STD_LOGIC
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)
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IS
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VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
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IF PARAM_value = '1' THEN
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UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
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ELSE
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UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
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END IF;
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END;
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PROCEDURE RESET_SM_STATUS(
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SIGNAL TX : OUT STD_LOGIC;
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SIGNAL RX : IN STD_LOGIC;
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CONSTANT tx_period : IN TIME;
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CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
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)
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IS
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BEGIN
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UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
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END;
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END lpp_lfr_sim_pkg;
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