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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity SelectInputs is
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generic(
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Input_SZ : integer := 16);
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port(
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clk : in std_logic;
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raz : in std_logic;
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Read : in std_logic;
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B1 : in std_logic_vector(Input_SZ-1 downto 0);
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B2 : in std_logic_vector(Input_SZ-1 downto 0);
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B3 : in std_logic_vector(Input_SZ-1 downto 0);
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E1 : in std_logic_vector(Input_SZ-1 downto 0);
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E2 : in std_logic_vector(Input_SZ-1 downto 0);
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Conjugate : out std_logic;
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Take : out std_logic;
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ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
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Statu : out std_logic_vector(3 downto 0);
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OP1 : out std_logic_vector(Input_SZ-1 downto 0);
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OP2 : out std_logic_vector(Input_SZ-1 downto 0)
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);
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end SelectInputs;
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architecture ar_SelectInputs of SelectInputs is
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signal Read_reg : std_logic;
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signal i : integer range 0 to 128;
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signal j : integer range 0 to 15;
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signal Read_int : std_logic_vector(4 downto 0);
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type state is (stX,sta,stb,st1,st2,idl1,idl2);
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signal ect : state;
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begin
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process(clk,raz)
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begin
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if(raz='0')then
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Take <= '0';
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i <= 0;
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j <= 0;
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Read_reg <= '0';
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ect <= stX;
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elsif(clk'event and clk='1')then
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Read_reg <= Read;
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case ect is
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when stX =>
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i <= 1;
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if(Read_reg='0' and Read='1')then
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if(j=15)then
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j <= 1;
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else
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j<= j+1;
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end if;
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ect <= idl1;
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end if;
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when idl1 =>
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ect <= st1;
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when st1 =>
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Take <= '1';
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ect <= sta;
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when sta =>
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if(Read_reg='0' and Read='1')then
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ect <= idl2;
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end if;
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when idl2 =>
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ect <= st2;
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when st2 =>
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Take <= '0';
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ect <= stb;
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when stb =>
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if(i=128)then
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ect <= stX;
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elsif(Read_reg='0' and Read='1')then
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i <= i+1;
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ect <= idl1;
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end if;
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end case;
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end if;
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end process;
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Statu <= std_logic_vector(to_unsigned(j,4));
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with j select
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Read_int <= "10000" when 1,
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"11000" when 2,
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"01000" when 3,
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"10100" when 4,
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"01100" when 5,
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"00100" when 6,
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"10010" when 7,
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"01010" when 8,
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"00110" when 9,
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"00010" when 10,
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"10001" when 11,
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"01001" when 12,
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"00101" when 13,
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"00011" when 14,
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"00001" when 15,
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"00000" when others;
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with ect select
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ReadFIFO <= Read_int when idl1,
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Read_int when idl2,
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"00000" when others;
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with j select
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OP1 <= B1 when 1,
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B1 when 2,
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B1 when 4,
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B1 when 7,
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B1 when 11,
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B2 when 3,
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B2 when 5,
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B2 when 8,
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B2 when 12,
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B3 when 6,
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B3 when 9,
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B3 when 13,
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E1 when 10,
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E1 when 14,
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E2 when 15,
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X"FFFF" when others;
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with j select
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OP2 <= B1 when 1,
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B2 when 2,
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B2 when 3,
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B3 when 4,
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B3 when 5,
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B3 when 6,
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E1 when 7,
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E1 when 8,
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E1 when 9,
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E1 when 10,
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E2 when 11,
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E2 when 12,
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E2 when 13,
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E2 when 14,
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E2 when 15,
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X"FFFF" when others;
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with j select
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Conjugate <= '1' when 1,
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'1' when 3,
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'1' when 6,
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'1' when 10,
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'1' when 15,
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'0' when others;
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end ar_SelectInputs;
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