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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY fifo_latency_correction IS
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_empty : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC
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);
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END fifo_latency_correction;
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ARCHITECTURE beh OF fifo_latency_correction IS
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SIGNAL valid_s1 : STD_LOGIC;
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SIGNAL valid_s2 : STD_LOGIC;
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SIGNAL data_s1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_s2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL dma_data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL ren_s1 : STD_LOGIC;
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SIGNAL ren_s2 : STD_LOGIC;
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SIGNAL fifo_ren_s : STD_LOGIC;
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BEGIN -- beh
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--fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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--fifo_empty : IN STD_LOGIC;
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--dma_ren : IN STD_LOGIC
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PROCESS (HCLK, HRESETn)
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BEGIN
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IF HRESETn = '0' THEN
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ren_s1 <= '1';
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ren_s2 <= '1';
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ELSIF HCLK'event AND HCLK = '1' THEN
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ren_s1 <= fifo_ren_s;
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ren_s2 <= fifo_ren_s;
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END IF;
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END PROCESS;
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fifo_ren <= fifo_ren_s;
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PROCESS (HCLK, HRESETn)
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BEGIN
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IF HRESETn = '0' THEN
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valid_s1 <= '0';
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--data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
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data_s1 <= (OTHERS => '0');
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ELSIF HCLK'event AND HCLK = '1' THEN
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IF valid_s1 = '0' THEN
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IF valid_s2 = '1' AND ren_s2 = '0' AND dma_ren = '1' THEN
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valid_s1 <= '1';
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data_s1 <= fifo_data;
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END IF;
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ELSE
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IF valid_s2 = '0' THEN
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IF ren_s2 = '0' AND dma_ren = '1' THEN
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valid_s1 <= '1';
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data_s1 <= fifo_data;
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ELSE
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valid_s1 <= '0';
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-- data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
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END IF;
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ELSE
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IF dma_ren = '1' THEN
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valid_s1 <= '1';
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data_s1 <= data_s1;
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ELSE
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IF ren_s2 = '0' THEN
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valid_s1 <= '1';
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data_s1 <= fifo_data;
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ELSE
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valid_s1 <= '0';
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-- data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (HCLK, HRESETn)
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BEGIN
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IF HRESETn = '0' THEN
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valid_s2 <= '0';
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-- data_s2 <= (OTHERS => 'X'); -- TODO just for simulation
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data_s2 <= (OTHERS => '0');
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ELSIF HCLK'event AND HCLK = '1' THEN
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IF valid_s2 = '0' THEN
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IF dma_ren = '1' THEN
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IF valid_s1 = '1' THEN
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valid_s2 <= '1';
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data_s2 <= data_s1;
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ELSE
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IF ren_s2 = '0' THEN
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valid_s2 <= '1';
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data_s2 <= fifo_data;
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END IF;
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END IF;
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END IF;
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ELSE
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IF dma_ren = '1' THEN
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valid_s2 <= '1';
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data_s2 <= data_s2;
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ELSE
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IF valid_s1 = '1' THEN
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valid_s2 <= '1';
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data_s2 <= data_s1;
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ELSE
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IF ren_s2 = '0' THEN
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valid_s2 <= '1';
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data_s2 <= fifo_data;
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ELSE
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valid_s2 <= '0';
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-- data_s2 <= (OTHERS => 'X'); -- TODO just for simulation
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-- PROCESS (HCLK, HRESETn)
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-- BEGIN
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-- IF HRESETn = '0' THEN
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-- dma_data <= (OTHERS => 'X');
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-- ELSIF HCLK'event AND HCLK = '1' THEN
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-- IF valid_s2 = '1' THEN
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-- dma_data <= data_s2;
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-- ELSIF valid_s1 = '1' THEN
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-- dma_data <= data_s1;
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-- ELSIF ren_s2 = '0' THEN
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-- dma_data <= fifo_data;
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-- ELSE
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-- dma_data <= (OTHERS => 'X');
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-- END IF;
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-- END IF;
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-- END PROCESS;
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dma_data_s <= data_s2 WHEN valid_s2 = '1' ELSE
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data_s1 WHEN valid_s1 = '1' ELSE
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fifo_data;
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PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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dma_data <= (OTHERS => '0');
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ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
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IF dma_ren = '0' THEN
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dma_data <= dma_data_s;
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END IF;
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END IF;
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END PROCESS;
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fifo_ren_s <= '1' WHEN fifo_empty = '1' ELSE
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-- '0' WHEN valid_s1 = '0' OR valid_s2 = '0' ELSE -- FIX test0
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'0' WHEN (valid_s1 = '0' OR valid_s2 = '0') AND ren_s2 = '1' ELSE -- FIX test0
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dma_ren;
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dma_empty <= fifo_empty AND (NOT valid_s1) AND (NOT valid_s2);
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END beh;
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