|
|
KEY LIBERO "9.1"
|
|
|
KEY CAPTURE "9.1.0.18"
|
|
|
KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
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|
|
KEY DEFAULT_OPEN_LOC ""
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|
|
KEY ProjectID "a358c50d-b636-4f4b-a666-2f198a8074ae"
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|
|
KEY HDLTechnology "VHDL"
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|
|
KEY VendorTechnology_Family "ProASIC3L"
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|
|
KEY VendorTechnology_Die "IT14X14M4LDP"
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|
|
KEY VendorTechnology_Package "fg324"
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|
|
KEY ProjectLocation "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon"
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|
|
KEY SimulationType "VHDL"
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|
|
KEY Vendor "Actel"
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|
|
KEY ActiveRoot "leon3mp::work"
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|
|
LIST REVISIONS
|
|
|
VALUE="Impl1",NUM=1
|
|
|
VALUE="Impl2",NUM=2
|
|
|
CURREV=2
|
|
|
ENDLIST
|
|
|
LIST LIBRARIES
|
|
|
grlib
|
|
|
synplify
|
|
|
techmap
|
|
|
spw
|
|
|
eth
|
|
|
opencores
|
|
|
gaisler
|
|
|
esa
|
|
|
fmf
|
|
|
spansion
|
|
|
gsi
|
|
|
lpp
|
|
|
cypress
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_grlib
|
|
|
ALIAS=grlib
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_synplify
|
|
|
ALIAS=synplify
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_techmap
|
|
|
ALIAS=techmap
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spw
|
|
|
ALIAS=spw
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_eth
|
|
|
ALIAS=eth
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_opencores
|
|
|
ALIAS=opencores
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gaisler
|
|
|
ALIAS=gaisler
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_esa
|
|
|
ALIAS=esa
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_fmf
|
|
|
ALIAS=fmf
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spansion
|
|
|
ALIAS=spansion
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gsi
|
|
|
ALIAS=gsi
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_lpp
|
|
|
ALIAS=lpp
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_cypress
|
|
|
ALIAS=cypress
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST FileManager
|
|
|
VALUE "<project>\..\..\boards\LeonLPP-A3PE3kL\Projet-LeonLFR-A3PE3kL-Sheldon.pdc,pdc"
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|
|
STATE="utd"
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|
|
TIME="1387451985"
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|
|
SIZE="16315"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
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|
|
SIZE="4857"
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|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="4684"
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|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2063"
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|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
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|
|
SIZE="2262"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl"
|
|
|
STATE="utd"
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|
|
TIME="1292248642"
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|
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SIZE="4068"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
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|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl"
|
|
|
STATE="utd"
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|
|
TIME="1292248642"
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|
|
SIZE="5400"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl"
|
|
|
STATE="utd"
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|
|
TIME="1292248642"
|
|
|
SIZE="4608"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2035"
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|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl"
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|
|
STATE="utd"
|
|
|
TIME="1292248642"
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|
|
SIZE="3093"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1366272480"
|
|
|
SIZE="7426"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1366031582"
|
|
|
SIZE="9480"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1374234887"
|
|
|
SIZE="11195"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1366724668"
|
|
|
SIZE="7704"
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|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1374234887"
|
|
|
SIZE="10813"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1348571754"
|
|
|
SIZE="2383"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1366619821"
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|
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SIZE="2637"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1374234887"
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SIZE="4306"
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|
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LIBRARY="lpp"
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|
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ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1374234887"
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|
|
SIZE="2748"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746407"
|
|
|
SIZE="141869"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746407"
|
|
|
SIZE="4032"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\APB_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1331642027"
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|
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SIZE="5929"
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\APB_FFT_half.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1332429937"
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|
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SIZE="5590"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
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|
|
STATE="utd"
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|
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TIME="1295516964"
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SIZE="12457"
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LIBRARY="lpp"
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ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
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|
|
STATE="utd"
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TIME="1362580136"
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SIZE="4110"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
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|
|
STATE="utd"
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|
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TIME="1373014223"
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SIZE="3532"
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LIBRARY="lpp"
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|
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ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\FFTamont.vhd,hdl"
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|
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STATE="utd"
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TIME="1362496295"
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SIZE="3702"
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LIBRARY="lpp"
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ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\FFTaval.vhd,hdl"
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|
|
STATE="utd"
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|
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TIME="1361890877"
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SIZE="2296"
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LIBRARY="lpp"
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ENDFILE
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|
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
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|
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STATE="utd"
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|
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TIME="1294746408"
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SIZE="25871"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
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|
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STATE="utd"
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TIME="1294746408"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
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|
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STATE="utd"
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TIME="1362564825"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Flag_Extremum.vhd,hdl"
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|
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STATE="utd"
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TIME="1373014151"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
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STATE="utd"
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TIME="1362580136"
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SIZE="3824"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
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STATE="utd"
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TIME="1374234887"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
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STATE="utd"
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TIME="1294746408"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
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|
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STATE="utd"
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TIME="1294746408"
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SIZE="12080"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Adder.vhd,hdl"
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|
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STATE="utd"
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TIME="1366976152"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
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|
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STATE="utd"
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TIME="1292248642"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
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STATE="utd"
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TIME="1366724668"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
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STATE="utd"
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TIME="1292248642"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
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STATE="utd"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\APB_AMR.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\bclk_reg.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\Clock_multi.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\Dephaseur.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\Gene_Rz.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_AMR\lpp_AMR.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_balise\APB_Balise.vhd,hdl"
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LIBRARY="lpp"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_balise\lpp_balise.vhd,hdl"
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STATE="utd"
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|
|
|
LiberoState=Post_Synthesis
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST AssociatedStimulus
|
|
|
ENDLIST
|
|
|
LIST Other_Association
|
|
|
ENDLIST
|
|
|
LIST SimulationOptions
|
|
|
UseAutomaticDoFile=true
|
|
|
IncludeWaveDo=false
|
|
|
Type=max
|
|
|
RunTime=1000ns
|
|
|
Resolution=1ps
|
|
|
VsimOpt=
|
|
|
EntityName=testbench
|
|
|
TopInstanceName=<top>_0
|
|
|
DoFileName=
|
|
|
DoFileName2=wave.do
|
|
|
DoFileParams=
|
|
|
DisplayDUTWave=false
|
|
|
LogAllSignals=false
|
|
|
DumpVCD=false
|
|
|
VCDFileName=power.vcd
|
|
|
ENDLIST
|
|
|
LIST ModelSimLibPath
|
|
|
UseCustomPath=FALSE
|
|
|
LibraryPath=
|
|
|
ENDLIST
|
|
|
LIST GlobalFlowOptions
|
|
|
GenerateHDLAfterSynthesis=FALSE
|
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
|
|
RunDRCAfterSynthesis=FALSE
|
|
|
AutoCheckConstraints=TRUE
|
|
|
UpdateViewDrawIni=TRUE
|
|
|
UpdateModelSimIni=TRUE
|
|
|
NoIOMode=FALSE
|
|
|
GenerateHDLFromSchematic=TRUE
|
|
|
FlashProInputFile=pdb
|
|
|
SmartGenCompileReport=T
|
|
|
ENDLIST
|
|
|
LIST PhySynthesisOptions
|
|
|
ENDLIST
|
|
|
LIST Profiles
|
|
|
NAME="Synplify AE"
|
|
|
FUNCTION="Synthesis"
|
|
|
TOOL="Synplify"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="ModelSim AE"
|
|
|
FUNCTION="Simulation"
|
|
|
TOOL="ModelSim"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="WFL"
|
|
|
FUNCTION="Stimulus"
|
|
|
TOOL="WFL"
|
|
|
LOCATION="syncad.exe"
|
|
|
PARAM="-pwflite"
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="FlashPro"
|
|
|
FUNCTION="Program"
|
|
|
TOOL="FlashPro"
|
|
|
LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
ENDLIST
|
|
|
LIST ProjectState5.1
|
|
|
LIST "leon3mp::work"
|
|
|
LIST Impl1
|
|
|
LiberoState=Post_Synthesis
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
LIST Impl2
|
|
|
LiberoState=Post_Synthesis
|
|
|
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
|
|
|
LIST FlowOptions
|
|
|
UsePhySynth=FALSE
|
|
|
UseSynth=TRUE
|
|
|
ENDLIST
|
|
|
Used_File_List
|
|
|
ENDUsed_File_List
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSimulation
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSynthesis
|
|
|
ENDLIST
|
|
|
LIST IncludeModuleForSimulation
|
|
|
ENDLIST
|
|
|
LIST CDBOrder
|
|
|
ENDLIST
|
|
|
LIST UserCustomizedFileList
|
|
|
ENDLIST
|
|
|
LIST OpenedFileList
|
|
|
DESIGNFLOW:
|
|
|
FILE:<project>\leon3mp.vhd,hdl
|
|
|
FILE:<project>\config.vhd,hdl
|
|
|
FILE:<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd,hdl
|
|
|
ACTIVE_VIEW:1
|
|
|
ENDLIST
|
|
|
|
