KEY LIBERO "9.1"
KEY CAPTURE "9.1.0.18"
KEY DEFAULT_IMPORT_LOC "D:\GRLIB_BusAMBA\VHD_Lib\lib\lpp\lpp_matrix"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "a358c50d-b636-4f4b-a666-2f198a8074ae"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "ProASIC3L"
KEY VendorTechnology_Die "IT14X14M4LDP"
KEY VendorTechnology_Package "fg324"
KEY ProjectLocation "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "leon3mp::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
grlib
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
ENDLIST
LIST LIBRARY_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\..\..\boards\LeonLPP-A3PE3kL\Projet-LeonLFR-A3PE3kL-Sheldon.pdc,pdc"
STATE="utd"
TIME="1387451985"
SIZE="16315"
ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl"
STATE="utd"
TIME="1292248642"
SIZE="4857"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl"
STATE="utd"
TIME="1292248642"
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LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
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ENDFILE
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ENDFILE
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
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VALUE "<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
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VALUE "<project>\synthesis\leon3mp_sdc.sdc,syn_sdc"
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ENDFILE
VALUE "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\boards\LeonLPP-A3PE3kL\Projet-LeonLFR-A3PE3kL-Sheldon.pdc,pdc"
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ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "leon3mp::work"
FILE "<project>\leon3mp.vhd,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify AE"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="ModelSim AE"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "leon3mp::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
LIST Impl2
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\leon3mp.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\leon3mp.vhd,hdl
FILE:<project>\config.vhd,hdl
FILE:<project>\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd,hdl
ACTIVE_VIEW:1
ENDLIST