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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ahbtbp
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-- File: ahbtbp.vhd
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-- Author: Nils-Johan Wessman - Gaisler Research
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-- Description: AHB Testbench package
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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package ahbtbp is
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type ahbtbm_ctrl_type is record
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delay : std_logic_vector(7 downto 0);
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dbgl : integer;
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reset : std_logic;
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use128 : integer;
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end record;
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type ahbtbm_access_type is record
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haddr : std_logic_vector(31 downto 0);
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hdata : std_logic_vector(31 downto 0);
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hdata128 : std_logic_vector(127 downto 0);
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htrans : std_logic_vector(1 downto 0);
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hburst : std_logic_vector(2 downto 0);
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hsize : std_logic_vector(2 downto 0);
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hprot : std_logic_vector(3 downto 0);
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hwrite : std_logic;
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ctrl : ahbtbm_ctrl_type;
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end record;
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type ahbtbm_status_type is record
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err : std_logic;
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ecount : std_logic_vector(15 downto 0);
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eaddr : std_logic_vector(31 downto 0);
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edatac : std_logic_vector(31 downto 0);
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edatar : std_logic_vector(31 downto 0);
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hresp : std_logic_vector(1 downto 0);
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end record;
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type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
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type ahbtbm_ctrl_in_type is record
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ac : ahbtbm_access_type;
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end record;
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type ahbtbm_ctrl_out_type is record
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rst : std_logic;
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clk : std_logic;
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update : std_logic;
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dvalid : std_logic;
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hrdata : std_logic_vector(31 downto 0);
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hrdata128 : std_logic_vector(127 downto 0);
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status : ahbtbm_status_type;
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end record;
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type ahbtb_ctrl_type is record
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i : ahbtbm_ctrl_in_type;
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o : ahbtbm_ctrl_out_type;
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end record;
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constant ac_idle : ahbtbm_access_type :=
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(haddr => x"00000000", hdata => x"00000000",
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hdata128 => x"00000000000000000000000000000000",
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htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
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ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
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constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
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constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
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update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
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status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
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edatac => (others => 'H'), edatar => (others => 'H'),
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hresp => (others => 'H')));
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impure function ptime return string;
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-- pragma translate_off
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-----------------------------------------------------------------------------
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-- AHB testbench Master
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-----------------------------------------------------------------------------
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component ahbtbm is
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generic (
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hindex : integer := 0;
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hirq : integer := 0;
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venid : integer := 0;
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devid : integer := 0;
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version : integer := 0;
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chprot : integer := 3;
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incaddr : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ctrli : in ahbtbm_ctrl_in_type;
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ctrlo : out ahbtbm_ctrl_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type
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);
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end component;
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-----------------------------------------------------------------------------
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-- AHB testbench Slave
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-----------------------------------------------------------------------------
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component ahbtbs is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#fff#;
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tech : integer := 0;
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kbytes : integer := 1);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end component;
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-----------------------------------------------------------------------------
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-- dprint (Debug print)
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-----------------------------------------------------------------------------
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procedure dprint(
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constant doprint : in boolean := true;
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constant s : in string);
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procedure dprint(
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constant s : in string);
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-----------------------------------------------------------------------------
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-- AMBATB Init
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-----------------------------------------------------------------------------
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procedure ahbtbminit(
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBATB DONE
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-----------------------------------------------------------------------------
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procedure ahbtbmdone(
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constant stop: in integer;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBATB Idle
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-----------------------------------------------------------------------------
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procedure ahbtbmidle(
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constant sync: in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure ahbwrite(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(31 downto 0);
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constant size : in std_logic_vector(1 downto 0);
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access (htrans)
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-----------------------------------------------------------------------------
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procedure ahbwrite(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(31 downto 0);
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constant size : in std_logic_vector(1 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahbwrite(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(31 downto 0);
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constant size : in std_logic_vector(1 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access (Inc Burst)
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-----------------------------------------------------------------------------
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procedure ahbwrite(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(31 downto 0);
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constant size : in std_logic_vector(1 downto 0);
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constant count : in integer;
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constant debug : in integer;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure ahbread(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(31 downto 0); -- Data
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constant size : in std_logic_vector(1 downto 0);
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access (htrans)
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-----------------------------------------------------------------------------
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procedure ahbread(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(31 downto 0); -- Data
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constant size : in std_logic_vector(1 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahbread(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(31 downto 0); -- Data
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constant size : in std_logic_vector(1 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access (Inc Burst)
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-----------------------------------------------------------------------------
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procedure ahbread(
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constant address : in std_logic_vector(31 downto 0); -- Start address
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constant data : in std_logic_vector(31 downto 0); -- Start data
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constant size : in std_logic_vector(1 downto 0);
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constant count : in integer;
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constant debug : in integer;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(128) write access (htrans)
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-----------------------------------------------------------------------------
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procedure ahb128write(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(127 downto 0);
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(128) write access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahb128write(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(127 downto 0);
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(128) read access (htrans)
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-----------------------------------------------------------------------------
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procedure ahb128read(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(127 downto 0); -- Data
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(128) read access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahb128read(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(127 downto 0); -- Data
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(64) write access (htrans)
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-----------------------------------------------------------------------------
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procedure ahb64write(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(63 downto 0);
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(64) write access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahb64write(
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constant address : in std_logic_vector(31 downto 0);
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constant data : in std_logic_vector(63 downto 0);
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(64) read access (htrans)
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-----------------------------------------------------------------------------
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procedure ahb64read(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(63 downto 0); -- Data
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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signal ctrl : inout ahbtb_ctrl_type);
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-----------------------------------------------------------------------------
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-- AMBA AHB(64) read access (htrans,hprot)
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-----------------------------------------------------------------------------
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procedure ahb64read(
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constant address : in std_logic_vector(31 downto 0); -- Address
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constant data : in std_logic_vector(63 downto 0); -- Data
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constant size : in std_logic_vector(2 downto 0);
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constant htrans : in std_logic_vector(1 downto 0);
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constant hburst : in std_logic;
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constant debug : in integer;
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constant appidle : in boolean;
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constant hprot : in std_logic_vector(3 downto 0);
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signal ctrl : inout ahbtb_ctrl_type);
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end ahbtbp;
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package body ahbtbp is
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impure function ptime return string is
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variable s : string(1 to 20);
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variable length : integer := tost(NOW / 1 ns)'length;
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begin
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s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
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return s(1 to length + 9);
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end function ptime;
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-----------------------------------------------------------------------------
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-- dprint (Debug print)
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-----------------------------------------------------------------------------
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procedure dprint(
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constant doprint : in boolean := true;
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constant s : in string) is
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begin
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if doprint = true then
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print(s);
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end if;
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end procedure dprint;
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procedure dprint(
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constant s : in string) is
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begin
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print(s);
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end procedure dprint;
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-----------------------------------------------------------------------------
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-- AHBTB init
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-----------------------------------------------------------------------------
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procedure ahbtbminit(
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signal ctrl : inout ahbtb_ctrl_type) is
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begin
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ctrl.o <= ctrlo_nodrive;
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ctrl.i <= ctrli_idle;
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--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
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--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
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--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
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wait until ctrl.o.rst = '1';
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print("**********************************************************");
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print(" AHBTBM Testbench Init");
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print("**********************************************************");
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end procedure ahbtbminit;
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-----------------------------------------------------------------------------
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-- AMBTB DONE
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-----------------------------------------------------------------------------
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|
|
procedure ahbtbmdone(
|
|
|
constant stop: in integer;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
print("**********************************************************");
|
|
|
print(" AHBTBM Testbench Done");
|
|
|
print("**********************************************************");
|
|
|
wait for 100 ns;
|
|
|
assert stop = 0
|
|
|
report "ahbtb testbench done!"
|
|
|
severity FAILURE;
|
|
|
end procedure ahbtbmdone;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBTB Idle
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbtbmidle(
|
|
|
constant sync: in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
if sync = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
end if;
|
|
|
end procedure ahbtbmidle;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB write access
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbwrite(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbwrite;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB write access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbwrite(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbwrite;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB write access (Inc Burst)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbwrite(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant count : in integer;
|
|
|
constant debug : in integer;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
variable vaddr : std_logic_vector(31 downto 0);
|
|
|
variable vdata : std_logic_vector(31 downto 0);
|
|
|
variable vhtrans : std_logic_vector(1 downto 0);
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
vaddr := address; vdata := data; vhtrans := "10";
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
for i in 0 to count - 1 loop
|
|
|
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
|
|
|
ctrl.i.ac.htrans <= vhtrans;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
vaddr := vaddr + x"4"; vdata := vdata + 1;
|
|
|
vhtrans := "11";
|
|
|
end loop;
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end procedure ahbwrite;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB write access (htrans,hprot)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbwrite(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbwrite;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB read access
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbread(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbread;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB read access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbread(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbread;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB read access (Inc Burst)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbread(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant count : in integer;
|
|
|
constant debug : in integer;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
variable vaddr : std_logic_vector(31 downto 0);
|
|
|
variable vdata : std_logic_vector(31 downto 0);
|
|
|
variable vhtrans : std_logic_vector(1 downto 0);
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
vaddr := address; vdata := data; vhtrans := "10";
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
for i in 0 to count - 1 loop
|
|
|
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
|
|
|
ctrl.i.ac.htrans <= vhtrans;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
vaddr := vaddr + x"4"; vdata := vdata + 1;
|
|
|
vhtrans := "11";
|
|
|
end loop;
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end procedure ahbread;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB read access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahbread(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(31 downto 0);
|
|
|
constant size : in std_logic_vector(1 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 0;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= '0' & size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahbread;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(128) write access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb128write(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(127 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb128write;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(128) write access (htrans,hprot)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb128write(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(127 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb128write;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(128) read access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb128read(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(127 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb128read;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(128) read access (htrans,hprot)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb128read(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(127 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb128read;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(64) write access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb64write(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(63 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb64write;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(64) write access (htrans,hprot)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb64write(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(63 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb64write;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(64) read access (htrans)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb64read(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(63 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= "1110";
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb64read;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- AMBA AHB(64) read access (htrans,hprot)
|
|
|
-----------------------------------------------------------------------------
|
|
|
procedure ahb64read(
|
|
|
constant address : in std_logic_vector(31 downto 0);
|
|
|
constant data : in std_logic_vector(63 downto 0);
|
|
|
constant size : in std_logic_vector(2 downto 0);
|
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
|
|
constant hburst : in std_logic;
|
|
|
constant debug : in integer;
|
|
|
constant appidle : in boolean;
|
|
|
constant hprot : in std_logic_vector(3 downto 0);
|
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
|
|
begin
|
|
|
--ctrl.o <= ctrlo_nodrive;
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i.ac.ctrl.use128 <= 1;
|
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
|
|
ctrl.i.ac.hsize <= size;
|
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
|
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
|
|
ctrl.i.ac.hprot <= hprot;
|
|
|
if appidle = true then
|
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
|
|
ctrl.i <= ctrli_idle;
|
|
|
end if;
|
|
|
end procedure ahb64read;
|
|
|
-- pragma translate_on
|
|
|
|
|
|
end ahbtbp;
|
|
|
|
|
|
|
