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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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--! \brief Universal shift register can be used to serialize or deserialize data.
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--!
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--! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
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--! \todo move to general purpose library, explain more in detail the code and add some schematic in doc.
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entity Shift_Reg is
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generic(
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Data_sz : integer := 10 --! Width of the shift register
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);
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port(
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Sclk : in std_logic; --! Serial clock
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SIN : in std_logic; --! Serial data in
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SOUT : out std_logic; --! Serial data out
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Serialize : in std_logic; --! Launch serialization
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Serialized : out std_logic; --! Serialization complete
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D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out
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Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data
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);
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end entity;
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architecture ar_Shift_Reg of Shift_Reg is
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signal REG : std_logic_vector(Data_sz-1 downto 0);
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signal CptBits : std_logic_vector(Data_sz-1 downto 0) := (others => '0');
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constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
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signal CptBits_flag : std_logic :='0';
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signal Serialized_int : std_logic :='1';
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begin
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CptBits_flag <= '1' when CptBits=CptBits_trig else '0';
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Serialized <= Serialized_int;
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process(Serialize,Sclk,D)
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begin
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if(Serialize = '1') then
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REG <= D;
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CptBits <= (others => '0');
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Serialized_int <= '0';
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Q <= REG;
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SOUT <= '1';
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elsif Sclk'event and Sclk = '1' then
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if(Serialized_int='0') then
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REG <= SIN & REG(Data_sz-1 downto 1);
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CptBits <= '1' & CptBits(Data_sz-1 downto 1);
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SOUT <= REG(0);
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if(CptBits_flag = '1') then
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Serialized_int <= '1';
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Q <= REG;
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end if;
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else
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SOUT <= '1';
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Serialized_int <= '1';
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-- Q <= REG;
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end if;
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end if;
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end process;
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end architecture;
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