HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_uart/Shift_REG.vhd

Correction de la FSM qui regule les données entrant dans la FFT

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        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

        Alexis
    
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              r38
            
      --                    Author : Alexis Jeandet

      --                     Mail : alexis.jeandet@lpp.polytechnique.fr

      ----------------------------------------------------------------------------

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      library IEEE;

      use IEEE.numeric_std.all;

      use IEEE.std_logic_1164.all;

        alexis
    
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              r67
            
      --! \brief Universal shift register can be used to serialize or deserialize data.

      --!

      --! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr

      --! \todo move to general purpose library, explain more in detail the code and add some schematic in doc.

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        martin
    
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              r99
            
      entity Shift_Reg is

        alexis
    
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              r67
            
      generic(

              Data_sz     :   integer :=  10 --! Width of the shift register

      );

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      port(

        alexis
    
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              r67
            
          Sclk        :   in  std_logic; --! Serial clock

          SIN         :   in  std_logic; --! Serial data in

          SOUT        :   out std_logic; --! Serial data out

          Serialize   :   in  std_logic; --! Launch serialization

          Serialized  :   out std_logic; --! Serialization complete

          D           :   in  std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out

          Q           :   out std_logic_vector(Data_sz-1 downto 0)  --! Unserialized data

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      );

      end entity;

        martin
    
Update and debug UART

              r99
            
      architecture ar_Shift_Reg of Shift_Reg is

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      signal   REG                :   std_logic_vector(Data_sz-1 downto 0);

        martin
    
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              r99
            
      signal   CptBits            :   std_logic_vector(Data_sz-1 downto 0) := (others => '0');

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      constant CptBits_trig       :   std_logic_vector(Data_sz-1 downto 0) := (others => '1');

        martin
    
Update and debug UART

              r99
            
      signal   CptBits_flag       :   std_logic :='0';

      signal   Serialized_int     :   std_logic :='1';

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      begin

        martin
    
Update and debug UART

              r99
            
      CptBits_flag    <= '1' when CptBits=CptBits_trig else '0';

      Serialized      <=  Serialized_int;

      process(Serialize,Sclk,D)

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      begin

        martin
    
Update and debug UART

              r99
            
          if(Serialize = '1') then

              REG <= D;

              CptBits <= (others => '0');

              Serialized_int  <= '0';

              Q           <=  REG;

              SOUT        <=  '1';

          elsif Sclk'event and Sclk = '1' then

              if(Serialized_int='0') then

                  REG         <=  SIN & REG(Data_sz-1 downto 1);

                  CptBits     <=  '1' & CptBits(Data_sz-1 downto 1);

                  SOUT        <=  REG(0);

                  if(CptBits_flag = '1') then

                      Serialized_int <= '1';

                      Q           <=  REG;

                  end if;

              else

                  SOUT        <=  '1';

                  Serialized_int <= '1';

      --            Q           <=  REG;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
              end if;

          end if;

      end process;

        martin
    
Update and debug UART

              r99
            
      end architecture;

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        martin
    
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              r99
            
        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        martin
    
Update and debug UART

              r99

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Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		-------------------------------------------------------------------------------
Alexis Minor changes	r38	-- Author : Alexis Jeandet
		-- Mail : alexis.jeandet@lpp.polytechnique.fr
		----------------------------------------------------------------------------
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	library IEEE;
		use IEEE.numeric_std.all;
		use IEEE.std_logic_1164.all;

alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	--! \brief Universal shift register can be used to serialize or deserialize data.
		--!
		--! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
		--! \todo move to general purpose library, explain more in detail the code and add some schematic in doc.
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
martin Update and debug UART	r99	entity Shift_Reg is
alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	generic(
		Data_sz : integer := 10 --! Width of the shift register
		);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	port(
alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	Sclk : in std_logic; --! Serial clock
		SIN : in std_logic; --! Serial data in
		SOUT : out std_logic; --! Serial data out
		Serialize : in std_logic; --! Launch serialization
		Serialized : out std_logic; --! Serialization complete
		D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out
		Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	);
		end entity;


martin Update and debug UART	r99	architecture ar_Shift_Reg of Shift_Reg is
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		signal REG : std_logic_vector(Data_sz-1 downto 0);
martin Update and debug UART	r99	signal CptBits : std_logic_vector(Data_sz-1 downto 0) := (others => '0');
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
martin Update and debug UART	r99	signal CptBits_flag : std_logic :='0';
		signal Serialized_int : std_logic :='1';
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		begin

martin Update and debug UART	r99	CptBits_flag <= '1' when CptBits=CptBits_trig else '0';
		Serialized <= Serialized_int;
		process(Serialize,Sclk,D)
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	begin
martin Update and debug UART	r99	if(Serialize = '1') then
		REG <= D;
		CptBits <= (others => '0');
		Serialized_int <= '0';
		Q <= REG;
		SOUT <= '1';
		elsif Sclk'event and Sclk = '1' then
		if(Serialized_int='0') then
		REG <= SIN & REG(Data_sz-1 downto 1);
		CptBits <= '1' & CptBits(Data_sz-1 downto 1);
		SOUT <= REG(0);
		if(CptBits_flag = '1') then
		Serialized_int <= '1';
		Q <= REG;
		end if;
		else
		SOUT <= '1';
		Serialized_int <= '1';
		-- Q <= REG;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	end if;
		end if;
		end process;

martin Update and debug UART	r99	end architecture;
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
martin Update and debug UART	r99


Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
martin Update and debug UART	r99