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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity RAM_WRITER is
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Generic(
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datawidth : integer := 18;
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abits : integer := 8
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);
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Port (
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clk : in STD_LOGIC; --! clk input
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rstn : in STD_LOGIC; --! Active low reset input
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DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector
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DATA_OUT : out STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA output vector
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WEN_IN : in STD_LOGIC; --! Active low Write Enable input
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WEN_OUT : out STD_LOGIC; --! Active low Write Enable output
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LOAD_ADDRESSN : in STD_LOGIC; --! Active low address load input
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ADDRESS_IN : in STD_LOGIC_VECTOR (abits-1 downto 0); --! Adress input vector
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ADDRESS_OUT : out STD_LOGIC_VECTOR (abits-1 downto 0) --! Adress output vector
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);
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end RAM_WRITER;
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architecture Behavioral of RAM_WRITER is
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signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
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begin
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ADDRESS_OUT <= ADDRESS_R;
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-- pass through connections for DATA and WEN
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DATA_OUT <= DATA_IN;
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WEN_OUT <= WEN_IN;
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process(clk,rstn)
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begin
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if rstn='0' then
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ADDRESS_R <= (others=>'0');
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elsif clk'event and clk='1' then
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if LOAD_ADDRESSN = '0' then
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ADDRESS_R <= ADDRESS_IN;
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elsif WEN_IN = '0' then
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ADDRESS_R <= STD_LOGIC_VECTOR(UNSIGNED(ADDRESS_R) + 1);
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end if;
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end if;
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end process;
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end Behavioral;
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