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DAC driver added, MINI-LFR design updated to be compatible with new leon3-soc.
Alexis Jeandet -
r530:5eb17174cdba JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.lpp_amba.all;
31 use lpp.lpp_cna.all;
32 use lpp.apb_devices_list.all;
33
34 entity apb_lfr_cal is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 tech : integer := 0;
40 PRESZ : integer := 8;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
44 abits : integer := 8
45 );
46 port (
47 rstn : in std_logic;
48 clk : in std_logic;
49 apbi : in apb_slv_in_type;
50 apbo : out apb_slv_out_type;
51 SDO : out std_logic;
52 SCK : out std_logic;
53 SYNC : out std_logic;
54 SMPCLK : out std_logic
55 );
56 end entity;
57
58 --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus
59 --! et les sorties seront cablοΏ½es vers le convertisseur.
60
61 architecture ar_apb_lfr_cal of apb_lfr_cal is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 signal pre : STD_LOGIC_VECTOR(PRESZ-1 downto 0);
70 signal N : STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
71 signal Reload : std_logic;
72 signal DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
73 signal WEN : STD_LOGIC;
74 signal LOAD_ADDRESSN : STD_LOGIC;
75 signal ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 downto 0);
76 signal ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 downto 0);
77 signal INTERLEAVED : STD_LOGIC;
78 signal DAC_CFG : STD_LOGIC_VECTOR(3 downto 0);
79 signal Rdata : std_logic_vector(31 downto 0);
80
81 begin
82
83 cal: lfr_cal_driver
84 generic map(
85 tech => tech,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
89 abits => abits
90 )
91 Port map(
92 clk => clk,
93 rstn => rstn,
94 pre => pre,
95 N => N,
96 Reload => Reload,
97 DATA_IN => DATA_IN,
98 WEN => WEN,
99 LOAD_ADDRESSN => LOAD_ADDRESSN,
100 ADDRESS_IN => ADDRESS_IN,
101 ADDRESS_OUT => ADDRESS_OUT,
102 INTERLEAVED => INTERLEAVED,
103 DAC_CFG => DAC_CFG,
104 SYNC => SYNC,
105 DOUT => SDO,
106 SCLK => SCK,
107 SMPCLK => SMPCLK
108 );
109
110 process(rstn,clk)
111 begin
112 if(rstn='0')then
113 pre <= (others=>'1');
114 N <= (others=>'1');
115 Reload <= '1';
116 DATA_IN <= (others=>'0');
117 WEN <= '1';
118 LOAD_ADDRESSN <= '1';
119 ADDRESS_IN <= (others=>'1');
120 INTERLEAVED <= '0';
121 DAC_CFG <= (others=>'0');
122 Rdata <= (others=>'0');
123 elsif(clk'event and clk='1')then
124
125
126 --APB Write OP
127 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
128 case apbi.paddr(abits-1 downto 2) is
129 when "000000" =>
130 DAC_CFG <= apbi.pwdata(3 downto 0);
131 Reload <= apbi.pwdata(4);
132 INTERLEAVED <= apbi.pwdata(5);
133 when "000001" =>
134 pre <= apbi.pwdata(PRESZ-1 downto 0);
135 when "000010" =>
136 N <= apbi.pwdata(CPTSZ-1 downto 0);
137 when "000011" =>
138 ADDRESS_IN <= apbi.pwdata(abits-1 downto 0);
139 LOAD_ADDRESSN <= '0';
140 when "000100" =>
141 DATA_IN <= apbi.pwdata(datawidth-1 downto 0);
142 WEN <= '0';
143 when others =>
144 null;
145 end case;
146 else
147 LOAD_ADDRESSN <= '1';
148 WEN <= '1';
149 end if;
150
151 --APB Read OP
152 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
153 case apbi.paddr(abits-1 downto 2) is
154 when "000000" =>
155 Rdata(3 downto 0) <= DAC_CFG;
156 Rdata(4) <= Reload;
157 Rdata(5) <= INTERLEAVED;
158 Rdata(31 downto 6) <= (others => '0');
159 when "000001" =>
160 Rdata(PRESZ-1 downto 0) <= pre;
161 Rdata(31 downto PRESZ) <= (others => '0');
162 when "000010" =>
163 Rdata(CPTSZ-1 downto 0) <= N;
164 Rdata(31 downto CPTSZ) <= (others => '0');
165 when "000011" =>
166 Rdata(abits-1 downto 0) <= ADDRESS_OUT;
167 Rdata(31 downto abits) <= (others => '0');
168 when "000100" =>
169 Rdata(datawidth-1 downto 0) <= DATA_IN;
170 Rdata(31 downto datawidth) <= (others => '0');
171 when others =>
172 Rdata <= (others => '0');
173 end case;
174 end if;
175
176 end if;
177 apbo.pconfig <= pconfig;
178 end process;
179
180 apbo.prdata <= Rdata when apbi.penable = '1';
181 end architecture ar_apb_lfr_cal; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
25
26 entity RAM_READER is
27 Generic(
28 datawidth : integer := 18;
29 dacresolution : integer := 12;
30 abits : integer := 8
31 );
32 Port (
33 clk : in STD_LOGIC; --! clock input
34 rstn : in STD_LOGIC; --! Active low restet input
35 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector -> connect to RAM DATA output
36 ADDRESS : out STD_LOGIC_VECTOR (abits-1 downto 0); --! ADDRESS output vector -> connect to RAM read ADDRESS input
37 REN : out STD_LOGIC; --! Active low read enable -> connect to RAM read enable
38 DATA_OUT : out STD_LOGIC_VECTOR (dacresolution-1 downto 0); --! DATA output vector
39 SMP_CLK : in STD_LOGIC; --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
40 INTERLEAVED : in STD_LOGIC --! When 1, interleaved mode is actived.
41 );
42 end RAM_READER;
43
44 architecture Behavioral of RAM_READER is
45 CONSTANT interleaved_sz : integer := dacresolution/(datawidth-dacresolution);
46
47 signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
48 signal SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
49 signal INTERLEAVED_SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
50 signal SMP_CLK_R : STD_LOGIC;
51 signal interleavedCNTR : integer range 0 to interleaved_sz;
52 signal REN_R : STD_LOGIC:='1';
53 signal interleave : STD_LOGIC:='0';
54 signal loadEvent : STD_LOGIC:='0';
55 signal loadEvent_R : STD_LOGIC:='0';
56 signal loadEvent_R2 : STD_LOGIC:='0';
57 begin
58
59 REN <= REN_R;
60 DATA_OUT <= SAMPLE_R;
61 ADDRESS <= ADDRESS_R;
62 interleave <= '1' when interleavedCNTR=interleaved_sz else '0';
63
64 loadEvent <= SMP_CLK and not SMP_CLK_R ;
65
66 process(clk,rstn)
67 begin
68 if rstn='0' then
69 SMP_CLK_R <= '0';
70 loadEvent_R <= '0';
71 loadEvent_R2 <= '0';
72 elsif clk'event and clk='1' then
73 SMP_CLK_R <= SMP_CLK;
74 loadEvent_R <= loadEvent;
75 loadEvent_R2 <= loadEvent_R;
76 end if;
77 end process;
78
79 process(clk,rstn)
80 begin
81 if rstn='0' then
82 ADDRESS_R <= (others=>'0');
83 SAMPLE_R <= (others=>'0');
84 INTERLEAVED_SAMPLE_R <= (others=>'0');
85 REN_R <= '1';
86 interleavedCNTR <= 0;
87 elsif clk'event and clk='1' then
88 if loadEvent = '1' then
89 if(interleave='0') then
90 REN_R <= '0';
91 end if;
92 else
93 REN_R <= '1';
94 end if;
95
96 if REN_R = '0' then
97 ADDRESS_R <= std_logic_vector(UNSIGNED(ADDRESS_R) + 1); --Automatic increment on each read
98 end if;
99
100 if loadEvent_R2='1' then
101 if(interleave='1') then
102 interleavedCNTR <= 0;
103 SAMPLE_R <= INTERLEAVED_SAMPLE_R;
104 else
105 if interleaved='1' then
106 interleavedCNTR <= interleavedCNTR + 1;
107 else
108 interleavedCNTR <= 0;
109 end if;
110 SAMPLE_R <= DATA_IN(dacresolution-1 downto 0);
111 INTERLEAVED_SAMPLE_R(dacresolution-1 downto 0) <= INTERLEAVED_SAMPLE_R(datawidth-dacresolution-1 downto 0) & DATA_IN(datawidth-1 downto dacresolution);
112 end if;
113 end if;
114 end if;
115 end process;
116
117 end Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
25
26 entity RAM_WRITER is
27 Generic(
28 datawidth : integer := 18;
29 abits : integer := 8
30 );
31 Port (
32 clk : in STD_LOGIC; --! clk input
33 rstn : in STD_LOGIC; --! Active low reset input
34 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector
35 DATA_OUT : out STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA output vector
36 WEN_IN : in STD_LOGIC; --! Active low Write Enable input
37 WEN_OUT : out STD_LOGIC; --! Active low Write Enable output
38 LOAD_ADDRESSN : in STD_LOGIC; --! Active low address load input
39 ADDRESS_IN : in STD_LOGIC_VECTOR (abits-1 downto 0); --! Adress input vector
40 ADDRESS_OUT : out STD_LOGIC_VECTOR (abits-1 downto 0) --! Adress output vector
41 );
42 end RAM_WRITER;
43
44 architecture Behavioral of RAM_WRITER is
45
46 signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
47 begin
48
49 ADDRESS_OUT <= ADDRESS_R;
50 -- pass through connections for DATA and WEN
51 DATA_OUT <= DATA_IN;
52 WEN_OUT <= WEN_IN;
53
54 process(clk,rstn)
55 begin
56 if rstn='0' then
57 ADDRESS_R <= (others=>'0');
58 elsif clk'event and clk='1' then
59 if LOAD_ADDRESSN = '0' then
60 ADDRESS_R <= ADDRESS_IN;
61 elsif WEN_IN = '0' then
62 ADDRESS_R <= STD_LOGIC_VECTOR(UNSIGNED(ADDRESS_R) + 1);
63 end if;
64 end if;
65 end process;
66
67 end Behavioral;
68
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22
23
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
26 use IEEE.NUMERIC_STD.ALL;
27
28 entity SPI_DAC_DRIVER is
29 Generic(
30 datawidth : INTEGER := 16;
31 MSBFIRST : INTEGER := 1
32 );
33 Port (
34 clk : in STD_LOGIC;
35 rstn : in STD_LOGIC;
36 DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
37 SMP_CLK : in STD_LOGIC;
38 SYNC : out STD_LOGIC;
39 DOUT : out STD_LOGIC;
40 SCLK : out STD_LOGIC
41 );
42 end entity SPI_DAC_DRIVER;
43
44 architecture behav of SPI_DAC_DRIVER is
45 signal SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
46 signal INPUTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
47 signal SMP_CLK_R : STD_LOGIC:='0';
48 signal shiftcnt : INTEGER:=0;
49 signal shifting : STD_LOGIC:='0';
50 signal shifting_R : STD_LOGIC:='0';
51 begin
52
53 DOUT <= SHIFTREG(datawidth-1);
54
55 MSB:IF MSBFIRST=1 GENERATE
56 INPUTREG <= DATA;
57 END GENERATE;
58
59 LSB:IF MSBFIRST=0 GENERATE
60 INPUTREG(datawidth-1 downto 0) <= DATA(0 to datawidth-1);
61 END GENERATE;
62
63 SCLK <= clk;
64
65 process(clk,rstn)
66 begin
67 if rstn='0' then
68 shifting_R <= '0';
69 SMP_CLK_R <= '0';
70 elsif clk'event and clk='1' then
71 SMP_CLK_R <= SMP_CLK;
72 shifting_R <= shifting;
73 end if;
74 end process;
75
76 process(clk,rstn)
77 begin
78 if rstn='0' then
79 shifting <= '0';
80 SHIFTREG <= (others=>'0');
81 SYNC <= '0';
82 shiftcnt <= 0;
83 elsif clk'event and clk='1' then
84 if(SMP_CLK='1' and SMP_CLK_R='0') then
85 SYNC <= '1';
86 shifting <= '1';
87 else
88 SYNC <= '0';
89 if shiftcnt = datawidth-1 then
90 shifting <= '0';
91 end if;
92 end if;
93 if shifting_R='1' then
94 shiftcnt <= shiftcnt + 1;
95 SHIFTREG <= SHIFTREG (datawidth-2 downto 0) & '0';
96 else
97 SHIFTREG <= INPUTREG;
98 shiftcnt <= 0;
99 end if;
100 end if;
101 end process;
102
103 end architecture behav;
104
105
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
25
26 entity dynamic_freq_div is
27 generic(
28 PRESZ : integer range 1 to 32:=4;
29 PREMAX : integer := 16#FFFFFF#;
30 CPTSZ : integer range 1 to 32:=16
31 );
32 Port (
33 clk : in STD_LOGIC;
34 rstn : in STD_LOGIC;
35 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
36 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
37 Reload : in std_logic;
38 clk_out : out STD_LOGIC
39 );
40 end dynamic_freq_div;
41
42 architecture Behavioral of dynamic_freq_div is
43 constant prescaller_reg_sz : integer := 2**PRESZ;
44 constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
45 signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0):=(others => '0');
47 signal internal_clk : std_logic:='0';
48 signal internal_clk_reg : std_logic:='0';
49 signal clk_out_reg : std_logic:='0';
50
51 begin
52
53 max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
54
55 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
56 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
57 end generate;
58 max1: if UNSIGNED(PREMAX_max) > PREMAX generate
59 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
60 prescaller_reg(PREMAX);
61 end generate;
62
63
64
65 prescaller: process(rstn, clk)
66 begin
67 if rstn='0' then
68 prescaller_reg <= (others => '0');
69 elsif clk'event and clk = '1' then
70 prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
71 end if;
72 end process;
73
74
75 clk_out <= clk_out_reg;
76
77 counter: process(rstn, clk)
78 begin
79 if rstn='0' then
80 cpt_reg <= (others => '0');
81 internal_clk_reg <= '0';
82 clk_out_reg <= '0';
83 elsif clk'event and clk = '1' then
84 internal_clk_reg <= internal_clk;
85 if Reload = '1' then
86 clk_out_reg <= '0';
87 cpt_reg <= (others => '0');
88 elsif (internal_clk = '1' and internal_clk_reg = '0') then
89 if cpt_reg = N then
90 clk_out_reg <= not clk_out_reg;
91 cpt_reg <= (others => '0');
92 else
93 cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
94 end if;
95 end if;
96 end if;
97 end process;
98
99 end Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 LIBRARY techmap;
25 USE techmap.gencomp.ALL;
26
27 library lpp;
28 use lpp.lpp_cna.all;
29
30
31 entity lfr_cal_driver is
32 generic(
33 tech : integer := 0;
34 PRESZ : integer range 1 to 32:=4;
35 PREMAX : integer := 16#FFFFFF#;
36 CPTSZ : integer range 1 to 32:=16;
37 datawidth : integer := 18;
38 abits : integer := 8
39 );
40 Port (
41 clk : in STD_LOGIC;
42 rstn : in STD_LOGIC;
43 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
44 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
45 Reload : in std_logic;
46 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
47 WEN : in STD_LOGIC;
48 LOAD_ADDRESSN : IN STD_LOGIC;
49 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
50 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
51 INTERLEAVED : IN STD_LOGIC;
52 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
53 SYNC : out STD_LOGIC;
54 DOUT : out STD_LOGIC;
55 SCLK : out STD_LOGIC;
56 SMPCLK : out STD_lOGIC
57 );
58 end lfr_cal_driver;
59
60 architecture Behavioral of lfr_cal_driver is
61 constant dacresolution : integer := 12;
62 signal RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
63 signal RAM_WEN : STD_LOGIC;
64 signal RAM_WADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
65 signal RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 downto 0);
66 signal RAM_RADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
67 signal RAM_REN : STD_LOGIC;
68 signal DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 downto 0);
69 signal SMP_CLK : STD_LOGIC;
70 signal DAC_INPUT : STD_LOGIC_VECTOR(15 downto 0);
71
72 begin
73
74 ADDRESS_OUT <= RAM_WADDR;
75 DAC_INPUT <= DAC_CFG & DAC_DATA;
76 SMPCLK <= SMP_CLK;
77
78 dac_drv: SPI_DAC_DRIVER
79 Generic map(
80 datawidth => 16,
81 MSBFIRST => 1
82 )
83 Port map(
84 clk => clk,
85 rstn => rstn,
86 DATA => DAC_INPUT,
87 SMP_CLK => SMP_CLK,
88 SYNC => SYNC,
89 DOUT => DOUT,
90 SCLK => SCLK
91 );
92
93 freqGen: dynamic_freq_div
94 generic map(
95 PRESZ => PRESZ,
96 PREMAX => PREMAX,
97 CPTSZ => CPTSZ
98 )
99 Port map( clk => clk,
100 rstn => rstn,
101 pre => pre,
102 N => N,
103 Reload => Reload,
104 clk_out => SMP_CLK
105 );
106
107
108 ramWr: RAM_WRITER
109 Generic map(
110 datawidth => datawidth,
111 abits => abits
112 )
113 Port map(
114 clk => clk,
115 rstn => rstn,
116 DATA_IN => DATA_IN,
117 DATA_OUT => RAM_DATA_IN,
118 WEN_IN => WEN,
119 WEN_OUT => RAM_WEN,
120 LOAD_ADDRESSN => LOAD_ADDRESSN,
121 ADDRESS_IN => ADDRESS_IN,
122 ADDRESS_OUT => RAM_WADDR
123 );
124
125 ramRd: RAM_READER
126 Generic map(
127 datawidth => datawidth,
128 dacresolution => dacresolution,
129 abits => abits
130 )
131 Port map(
132 clk => clk,
133 rstn => rstn,
134 DATA_IN => RAM_DATA_OUT,
135 ADDRESS => RAM_RADDR,
136 REN => RAM_REN,
137 DATA_OUT => DAC_DATA,
138 SMP_CLK => SMP_CLK,
139 INTERLEAVED => INTERLEAVED
140 );
141
142 SRAM : syncram_2p
143 GENERIC MAP(tech, abits, datawidth)
144 PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
145
146 end Behavioral;
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@@ -140,6 +140,9 ARCHITECTURE beh OF MINI_LFR_top IS
140 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
140 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
141 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
141 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
142
142
143 SIGNAL SRAM_CE_V : STD_LOGIC_VECTOR(1 downto 0);
144
145
143 BEGIN -- beh
146 BEGIN -- beh
144
147
145 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
@@ -262,8 +265,9 BEGIN -- beh
262 nSRAM_BE2 => SRAM_nBE(2),
265 nSRAM_BE2 => SRAM_nBE(2),
263 nSRAM_BE3 => SRAM_nBE(3),
266 nSRAM_BE3 => SRAM_nBE(3),
264 nSRAM_WE => SRAM_nWE,
267 nSRAM_WE => SRAM_nWE,
265 nSRAM_CE => SRAM_CE,
268 nSRAM_CE => SRAM_CE_V,
266 nSRAM_OE => SRAM_nOE,
269 nSRAM_OE => SRAM_nOE,
270 nSRAM_READY=> open,
267
271
268 apbi_ext => apbi_ext,
272 apbi_ext => apbi_ext,
269 apbo_ext => apbo_ext,
273 apbo_ext => apbo_ext,
@@ -271,5 +275,7 BEGIN -- beh
271 ahbo_s_ext => ahbo_s_ext,
275 ahbo_s_ext => ahbo_s_ext,
272 ahbi_m_ext => ahbi_m_ext,
276 ahbi_m_ext => ahbi_m_ext,
273 ahbo_m_ext => ahbo_m_ext);
277 ahbo_m_ext => ahbo_m_ext);
278
279 SRAM_CE <= SRAM_CE_V(0);
274
280
275 END beh;
281 END beh;
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@@ -31,6 +31,127 use lpp.lpp_amba.all;
31
31
32 package lpp_cna is
32 package lpp_cna is
33
33
34 component apb_lfr_cal is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 tech : integer := 0;
40 PRESZ : integer := 8;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
44 abits : integer := 8);
45 port (
46 rstn : in std_logic;
47 clk : in std_logic;
48 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type;
50 SDO : out std_logic;
51 SCK : out std_logic;
52 SYNC : out std_logic;
53 SMPCLK : out std_logic
54 );
55 end component;
56
57 component SPI_DAC_DRIVER is
58 Generic(
59 datawidth : INTEGER := 16;
60 MSBFIRST : INTEGER := 1
61 );
62 Port (
63 clk : in STD_LOGIC;
64 rstn : in STD_LOGIC;
65 DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
66 SMP_CLK : in STD_LOGIC;
67 SYNC : out STD_LOGIC;
68 DOUT : out STD_LOGIC;
69 SCLK : out STD_LOGIC
70 );
71 end component;
72
73 component dynamic_freq_div is
74 generic(
75 PRESZ : integer range 1 to 32:=4;
76 PREMAX : integer := 16#FFFFFF#;
77 CPTSZ : integer range 1 to 32:=16
78 );
79 Port (
80 clk : in STD_LOGIC;
81 rstn : in STD_LOGIC;
82 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
83 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
84 Reload : in std_logic;
85 clk_out : out STD_LOGIC
86 );
87 end component;
88
89 component lfr_cal_driver is
90 generic(
91 tech : integer := 0;
92 PRESZ : integer range 1 to 32:=4;
93 PREMAX : integer := 16#FFFFFF#;
94 CPTSZ : integer range 1 to 32:=16;
95 datawidth : integer := 18;
96 abits : integer := 8
97 );
98 Port (
99 clk : in STD_LOGIC;
100 rstn : in STD_LOGIC;
101 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
102 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
103 Reload : in std_logic;
104 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
105 WEN : in STD_LOGIC;
106 LOAD_ADDRESSN : IN STD_LOGIC;
107 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
108 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
109 INTERLEAVED : IN STD_LOGIC;
110 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
111 SYNC : out STD_LOGIC;
112 DOUT : out STD_LOGIC;
113 SCLK : out STD_LOGIC;
114 SMPCLK : out STD_lOGIC
115 );
116 end component;
117
118 component RAM_READER is
119 Generic(
120 datawidth : integer := 18;
121 dacresolution : integer := 12;
122 abits : integer := 8
123 );
124 Port (
125 clk : in STD_LOGIC; --! clock input
126 rstn : in STD_LOGIC; --! Active low restet input
127 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector -> connect to RAM DATA output
128 ADDRESS : out STD_LOGIC_VECTOR (abits-1 downto 0); --! ADDRESS output vector -> connect to RAM read ADDRESS input
129 REN : out STD_LOGIC; --! Active low read enable -> connect to RAM read enable
130 DATA_OUT : out STD_LOGIC_VECTOR (dacresolution-1 downto 0); --! DATA output vector
131 SMP_CLK : in STD_LOGIC; --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
132 INTERLEAVED : in STD_LOGIC --! When 1, interleaved mode is actived.
133 );
134 end component;
135
136
137 component RAM_WRITER is
138 Generic(
139 datawidth : integer := 18;
140 abits : integer := 8
141 );
142 Port (
143 clk : in STD_LOGIC; --! clk input
144 rstn : in STD_LOGIC; --! Active low reset input
145 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector
146 DATA_OUT : out STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA output vector
147 WEN_IN : in STD_LOGIC; --! Active low Write Enable input
148 WEN_OUT : out STD_LOGIC; --! Active low Write Enable output
149 LOAD_ADDRESSN : in STD_LOGIC; --! Active low address load input
150 ADDRESS_IN : in STD_LOGIC_VECTOR (abits-1 downto 0); --! Adress input vector
151 ADDRESS_OUT : out STD_LOGIC_VECTOR (abits-1 downto 0) --! Adress output vector
152 );
153 end component;
154
34 component APB_DAC is
155 component APB_DAC is
35 generic (
156 generic (
36 pindex : integer := 0;
157 pindex : integer := 0;
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