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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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ENTITY coarse_time_counter IS
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GENERIC (
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NB_SECOND_DESYNC : INTEGER := 60);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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tick : IN STD_LOGIC;
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set_TCU : IN STD_LOGIC;
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new_TCU : IN STD_LOGIC;
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set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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CT_add1 : IN STD_LOGIC;
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fsm_desync : IN STD_LOGIC;
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FT_max : IN STD_LOGIC;
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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coarse_time_new : OUT STD_LOGIC
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);
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END coarse_time_counter;
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ARCHITECTURE beh OF coarse_time_counter IS
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SIGNAL add1_bit31 : STD_LOGIC;
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SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
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SIGNAL coarse_time_new_counter : STD_LOGIC;
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SIGNAL coarse_time_31 : STD_LOGIC;
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SIGNAL coarse_time_31_reg : STD_LOGIC;
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SIGNAL set_synchronized : STD_LOGIC;
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SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
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--CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
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SIGNAL set_TCU_reg : STD_LOGIC;
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BEGIN -- beh
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-----------------------------------------------------------------------------
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-- COARSE_TIME( 30 DOWNTO 0)
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-----------------------------------------------------------------------------
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counter_1 : general_counter
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GENERIC MAP (
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CYCLIC => '1',
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NB_BITS_COUNTER => 31,
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RST_VALUE => 0)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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MAX_VALUE => "111" & X"FFFFFFF" ,
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set => set_TCU_reg,
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set_value => set_TCU_value(30 DOWNTO 0),
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add1 => CT_add1,
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counter => coarse_time(30 DOWNTO 0));
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add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
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-----------------------------------------------------------------------------
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-- COARSE_TIME(31)
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-----------------------------------------------------------------------------
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--set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
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--set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
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-- (OTHERS => '0');
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set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
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set_synchronized_value <= (OTHERS => '0');
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counter_2 : general_counter
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GENERIC MAP (
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CYCLIC => '0',
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NB_BITS_COUNTER => 6,
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RST_VALUE => NB_SECOND_DESYNC
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)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
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set => set_synchronized,
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set_value => set_synchronized_value,
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add1 => add1_bit31,
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counter => nb_second_counter);
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coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
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coarse_time(31) <= coarse_time_31;
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coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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coarse_time_new_counter <= '0';
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coarse_time_31_reg <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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coarse_time_31_reg <= coarse_time_31;
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IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
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coarse_time_new_counter <= '1';
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ELSE
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coarse_time_new_counter <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- Just to try to limit the constraint
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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set_TCU_reg <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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set_TCU_reg <= set_TCU;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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END beh;
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