HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/Rocket_PCM_Encoder/Word_Cntr.vhd

Correction de la FSM qui regule les données entrant dans la FFT

Alexis Jeandet - - Load All Authors

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r219:df1aff8cd31b alexis


                r557:7faec0eb9fbb

(MINI-LFR) WFP_MS-0-1-67 (LFR-EM) WFP_MS_1-1-67 JC

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             Word_Cntr.vhd
        
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      -- Word_Cntr.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity Word_Cntr is

      generic(WordSize :integer := 8 ;N   :   integer := 144);

      port(

          Sclk    :   in  std_logic;

          reset   :   in  std_logic;

          WordClk :   out std_logic;

          Cnt_out :   out integer range 0 to N-1

      );

      end entity;

      architecture ar_Word_Cntr of Word_Cntr is

      signal  Cnt_int     :   integer range 0 to N-1 := 0;

      signal  Wcnt        :   integer range 0 to WordSize -1 ;

      begin

      Cnt_out <=  Cnt_int;

      process(Sclk,reset)

      begin

          if reset = '0' then

              Cnt_int <= 0;

              Wcnt    <=  0;

              WordClk <=  '0';

          elsif Sclk'event and Sclk = '1' then

              if Wcnt = WordSize - 1 then

                  if Cnt_int = N-1 then

                      Cnt_int <= 0;

                  else

                      Cnt_int <=  Cnt_int + 1;

                  end if;

                  Wcnt    <=  0;

                  WordClk <=  '1';

              else

                  Wcnt    <=  Wcnt + 1;

                  WordClk <=  '0';

              end if;

          end if;

      end process;

      end ar_Word_Cntr;

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				-- Word_Cntr.vhd
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;




				entity Word_Cntr is
				generic(WordSize :integer := 8 ;N : integer := 144);
				port(
				Sclk : in std_logic;
				reset : in std_logic;
				WordClk : out std_logic;
				Cnt_out : out integer range 0 to N-1
				);
				end entity;



				architecture ar_Word_Cntr of Word_Cntr is

				signal Cnt_int : integer range 0 to N-1 := 0;
				signal Wcnt : integer range 0 to WordSize -1 ;

				begin

				Cnt_out <= Cnt_int;

				process(Sclk,reset)
				begin
				if reset = '0' then
				Cnt_int <= 0;
				Wcnt <= 0;
				WordClk <= '0';
				elsif Sclk'event and Sclk = '1' then
				if Wcnt = WordSize - 1 then
				if Cnt_int = N-1 then
				Cnt_int <= 0;
				else
				Cnt_int <= Cnt_int + 1;
				end if;
				Wcnt <= 0;
				WordClk <= '1';
				else
				Wcnt <= Wcnt + 1;
				WordClk <= '0';
				end if;
				end if;
				end process;
				end ar_Word_Cntr;