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# Top Level Design Parameters
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# Clocks
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create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
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create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
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#create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
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create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
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create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
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#create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
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# False Paths Between Clocks
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# False Path Constraints
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# Maximum Delay Constraints
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# Multicycle Constraints
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# Virtual Clocks
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# Output Load Constraints
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# Driving Cell Constraints
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# Wire Loads
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# set_wire_load_mode top
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# Other Constraints
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## GRSPW constraints
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create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
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create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
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set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
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set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
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## set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
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## set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
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## set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
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## set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout ## > max 20ns
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## set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
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## set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
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