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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY std;
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use std.textio.all;
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ENTITY data_write_with_burstCounter IS
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GENERIC (
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OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
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NB_CHAR_PER_DATA : INTEGER := 4;
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BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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burst_valid : IN STD_LOGIC;
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burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_ren : OUT STD_LOGIC;
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data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
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close_file : IN STD_LOGIC
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);
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END;
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ARCHITECTURE beh OF data_write_with_burstCounter IS
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COMPONENT data_write
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GENERIC (
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OUTPUT_FILE_NAME : STRING;
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NB_CHAR_PER_DATA : INTEGER );
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PORT (
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clk : IN STD_LOGIC;
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data_in_val : IN STD_LOGIC;
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data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
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close_file : IN STD_LOGIC);
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END COMPONENT;
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SIGNAL ren_counter : INTEGER;
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SIGNAL data_ren_s : STD_LOGIC;
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SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_in_val : STD_LOGIC;
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BEGIN
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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ren_counter <= 0;
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data_ren_s <= '1';
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data_s <= (OTHERS => '0');
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data_in_val <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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data_s <= data;
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data_ren_s <= '1';
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IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN
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ren_counter <= 16;
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END IF;
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IF ren_counter > 0 THEN
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ren_counter <= ren_counter - 1;
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data_ren_s <= '0';
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END IF;
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data_in_val <= NOT data_ren_s;
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END IF;
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END PROCESS;
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data_ren <= data_ren_s;
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data_write_1: data_write
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GENERIC MAP (
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OUTPUT_FILE_NAME => OUTPUT_FILE_NAME,
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NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
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PORT MAP (
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clk => clk,
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data_in_val => data_in_val,
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data => data,
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close_file => close_file);
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END beh;
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