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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.lpp_memory.ALL;
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--USE lpp.lpp_uart.ALL;
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USE lpp.lpp_matrix.ALL;
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--USE lpp.lpp_delay.ALL;
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USE lpp.lpp_fft.ALL;
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USE lpp.fft_components.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.Filtercfg.ALL;
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USE lpp.lpp_demux.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_Header.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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ENTITY lpp_lfr_ms IS
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GENERIC (
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Mem_use : INTEGER
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- DATA INPUT
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---------------------------------------------------------------------------
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-- TIME
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coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
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fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
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--
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sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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--
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sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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--
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sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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---------------------------------------------------------------------------
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-- DMA
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---------------------------------------------------------------------------
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_valid : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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-- Reg out
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- Reg In
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status_ready_matrix_f0_0 :IN STD_LOGIC;
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status_ready_matrix_f0_1 :IN STD_LOGIC;
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status_ready_matrix_f1 :IN STD_LOGIC;
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status_ready_matrix_f2 :IN STD_LOGIC;
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status_error_anticipating_empty_fifo :IN STD_LOGIC;
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status_error_bad_component_error :IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END;
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ARCHITECTURE Behavioral OF lpp_lfr_ms IS
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-----------------------------------------------------------------------------
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SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL FFT_Load : STD_LOGIC;
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SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL SM_FlagError : STD_LOGIC;
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-- SIGNAL SM_Pong : STD_LOGIC;
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SIGNAL SM_Wen : STD_LOGIC;
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SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL Head_Empty : STD_LOGIC;
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SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL Head_Valid : STD_LOGIC;
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SIGNAL Head_Val : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL DMA_Read : STD_LOGIC;
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SIGNAL DMA_ack : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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Memf0: lppFIFOxN
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GENERIC MAP (
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tech => 0, Mem_use => Mem_use, Data_sz => 16,
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Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP (
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rstn => rstn, wclk => clk, rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
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wdata => sample_f0_wdata, rdata => FifoF0_Data,
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full => OPEN, empty => FifoF0_Empty);
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Memf1: lppFIFOxN
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GENERIC MAP (
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tech => 0, Mem_use => Mem_use, Data_sz => 16,
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Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP (
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rstn => rstn, wclk => clk, rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
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wdata => sample_f1_wdata, rdata => FifoF1_Data,
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full => OPEN, empty => FifoF1_Empty);
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Memf2: lppFIFOxN
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GENERIC MAP (
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tech => 0, Mem_use => Mem_use, Data_sz => 16,
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Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP (
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rstn => rstn, wclk => clk, rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
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wdata => sample_f3_wdata, rdata => FifoF3_Data,
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full => OPEN, empty => FifoF3_Empty);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DMUX0 : DEMUX
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GENERIC MAP (
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Data_sz => 16)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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Read => FFT_Read,
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Load => FFT_Load,
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EmptyF0 => FifoF0_Empty,
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EmptyF1 => FifoF1_Empty,
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EmptyF2 => FifoF3_Empty,
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DataF0 => FifoF0_Data,
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DataF1 => FifoF1_Data,
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DataF2 => FifoF3_Data,
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WorkFreq => DMUX_WorkFreq,
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Read_DEMUX => DMUX_Read,
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Empty => DMUX_Empty,
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Data => DMUX_Data);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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FFT0: FFT
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GENERIC MAP (
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Data_sz => 16,
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NbData => 256)
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PORT MAP (
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clkm => clk,
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rstn => rstn,
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FifoIN_Empty => DMUX_Empty,
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FifoIN_Data => DMUX_Data,
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FifoOUT_Full => FifoINT_Full,
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Load => FFT_Load,
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Read => FFT_Read,
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Write => FFT_Write,
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ReUse => FFT_ReUse,
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Data => FFT_Data);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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MemInt : lppFIFOxN
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GENERIC MAP (
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tech => 0,
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Mem_use => Mem_use,
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Data_sz => 16,
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Addr_sz => 8,
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FifoCnt => 5,
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Enable_ReUse => '1')
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PORT MAP (
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rstn => rstn,
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wclk => clk,
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rclk => clk,
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ReUse => SM_ReUse,
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wen => FFT_Write,
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ren => SM_Read,
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wdata => FFT_Data,
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rdata => FifoINT_Data,
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full => FifoINT_Full,
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empty => OPEN);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SM0 : MatriceSpectrale
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GENERIC MAP (
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Input_SZ => 16,
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Result_SZ => 32)
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PORT MAP (
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clkm => clk,
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rstn => rstn,
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FifoIN_Full => FifoINT_Full,
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SetReUse => FFT_ReUse,
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Valid => Head_Valid,
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Data_IN => FifoINT_Data,
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ACK => DMA_ack,
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SM_Write => SM_Wen,
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FlagError => SM_FlagError,
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-- Pong => SM_Pong,
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Statu => SM_Param,
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Write => SM_Write,
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Read => SM_Read,
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ReUse => SM_ReUse,
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Data_OUT => SM_Data);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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MemOut : lppFIFOxN
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GENERIC MAP (
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tech => 0,
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Mem_use => Mem_use,
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Data_sz => 32,
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Addr_sz => 8,
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FifoCnt => 2,
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Enable_ReUse => '0')
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PORT MAP (
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rstn => rstn,
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wclk => clk,
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rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => SM_Write,
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ren => Head_Read,
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wdata => SM_Data,
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rdata => FifoOUT_Data,
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full => FifoOUT_Full,
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empty => FifoOUT_Empty);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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Head0 : HeaderBuilder
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GENERIC MAP (
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Data_sz => 32)
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PORT MAP (
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clkm => clk,
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rstn => rstn,
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-- pong => SM_Pong,
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Statu => SM_Param,
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Matrix_Type => DMUX_WorkFreq,
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Matrix_Write => SM_Wen,
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Valid => Head_Valid,
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dataIN => FifoOUT_Data,
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emptyIN => FifoOUT_Empty,
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RenOUT => Head_Read,
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dataOUT => Head_Data,
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emptyOUT => Head_Empty,
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RenIN => DMA_Read,
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header => Head_Header,
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header_val => Head_Val,
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header_ack => DMA_ack );
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-----------------------------------------------------------------------------
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data_time(31 DOWNTO 0) <= coarse_time;
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data_time(47 DOWNTO 32) <= fine_time;
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lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
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PORT MAP (
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HCLK => clk,
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HRESETn => rstn,
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data_time => data_time,
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fifo_data => Head_Data,
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fifo_empty => Head_Empty,
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fifo_ren => DMA_Read,
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header => Head_Header,
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header_val => Head_Val,
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header_ack => DMA_ack,
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dma_addr => dma_addr,
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dma_data => dma_data,
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dma_valid => dma_valid,
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dma_valid_burst => dma_valid_burst,
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dma_ren => dma_ren,
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dma_done => dma_done,
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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debug_reg => debug_reg,
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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config_active_interruption_onError => config_active_interruption_onError,
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addr_matrix_f0_0 => addr_matrix_f0_0,
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addr_matrix_f0_1 => addr_matrix_f0_1,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2);
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-----------------------------------------------------------------------------
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--lpp_dma_ip_1: lpp_dma_ip
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-- GENERIC MAP (
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-- tech => 0,
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-- hindex => hindex)
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-- PORT MAP (
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-- HCLK => clk,
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-- HRESETn => rstn,
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-- AHB_Master_In => AHB_Master_In,
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-- AHB_Master_Out => AHB_Master_Out,
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-- fifo_data => Head_Data,
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-- fifo_empty => Head_Empty,
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-- fifo_ren => DMA_Read,
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-- header => Head_Header,
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-- header_val => Head_Val,
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-- header_ack => DMA_ack,
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-- ready_matrix_f0_0 => ready_matrix_f0_0,
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-- ready_matrix_f0_1 => ready_matrix_f0_1,
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-- ready_matrix_f1 => ready_matrix_f1,
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-- ready_matrix_f2 => ready_matrix_f2,
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-- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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-- error_bad_component_error => error_bad_component_error,
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-- debug_reg => debug_reg,
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-- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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-- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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-- status_ready_matrix_f1 => status_ready_matrix_f1,
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-- status_ready_matrix_f2 => status_ready_matrix_f2,
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-- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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-- status_error_bad_component_error => status_error_bad_component_error,
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-- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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-- config_active_interruption_onError => config_active_interruption_onError,
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-- addr_matrix_f0_0 => addr_matrix_f0_0,
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-- addr_matrix_f0_1 => addr_matrix_f0_1,
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-- addr_matrix_f1 => addr_matrix_f1,
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-- addr_matrix_f2 => addr_matrix_f2);
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-------------------------------------------------------------------------------
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END Behavioral;
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