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-- FFTamont.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity FFTamont is
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generic(
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Data_sz : integer range 1 to 32 := 16;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Load : in std_logic;
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Empty : in std_logic;
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DATA : in std_logic_vector(Data_sz-1 downto 0);
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Valid : out std_logic;
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Read : out std_logic;
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Data_re : out std_logic_vector(Data_sz-1 downto 0);
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Data_im : out std_logic_vector(Data_sz-1 downto 0)
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);
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end entity;
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architecture ar_FFTamont of FFTamont is
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type etat is (eX,e0,e1,e2);
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signal ect : etat;
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signal DataCount : integer;
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begin
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process(clk,rstn)
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begin
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if(rstn='0')then
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ect <= e0;
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Read <= '1';
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Valid <= '0';
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Data_re <= (others => '0');
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Data_im <= (others => '0');
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DataCount <= 0;
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elsif(clk'event and clk='1')then
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case ect is
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when e0 =>
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if(Load='1' and Empty='0')then
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Read <= '0';
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ect <= e1;
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end if;
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when e1 =>
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Valid <= '0';
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Read <= '1';
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ect <= e2;
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when e2 =>
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Data_re <= DATA;
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Data_im <= (others => '0');
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Valid <= '1';
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if(DataCount=NbData-1)then
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DataCount <= 0;
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ect <= eX;
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else
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DataCount <= DataCount + 1;
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if(Load='1' and Empty='0')then
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Read <= '0';
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ect <= e1;
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else
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ect <= eX;
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end if;
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end if;
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when eX =>
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Valid <= '0';
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ect <= e0;
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when others =>
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null;
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end case;
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--***********************************************************
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-- Chargement Rapide (toutes a la suite)
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--***********************************************************
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-- case ect is
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--
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-- when e0 =>
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-- if(Load='1' and Empty='0')then
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-- Read <= '0';
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-- ect <= eX;
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-- end if;
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--
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-- when eX =>
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-- ect <= e1;
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--
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-- when e1 =>
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-- Data_re <= DATA;
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-- Data_im <= (others => '0');
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-- Valid <= '1';
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-- if(DataCount=NbData-2)then
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-- Read <= '1';
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-- DataCount <= DataCount + 1;
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-- elsif(DataCount=NbData)then
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-- Valid <= '0';
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-- DataCount <= 0;
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-- ect <= e0;
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-- else
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-- DataCount <= DataCount + 1;
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-- end if;
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--
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-- when others =>
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-- null;
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--
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-- end case;
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--***********************************************************
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end if;
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end process;
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end architecture;
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