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- Thu, 11 Apr 2013 15:01:51
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designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Makefile
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#GRLIB=../..
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TOP = leon3mp
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BOARD = Projet-LeonLFR-A3P3K-Sheldon
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE = $( PART ) - $( PACKAGE )$( SPEED )
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UCF = $( GRLIB ) /boards/ $( BOARD ) / $( TOP ) .ucf
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QSF = $( GRLIB ) /boards/ $( BOARD ) / $( TOP ) .qsf
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EFFORT = high
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XSTOPT =
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SYNPOPT = "set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
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VHDLSYNFILES = config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd
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VHDLSIMFILES = testbench.vhd TB_Data_Acquisition.vhd
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SIMTOP = testbench
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SDCFILE = $( GRLIB ) /boards/ $( BOARD ) /synplify.sdc
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SDC = $( GRLIB ) /boards/ $( BOARD ) /leon3mp.sdc
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PDC = $( GRLIB ) /boards/ $( BOARD ) /Projet-LeonLFR-A3P3K-Sheldon.pdc
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BITGEN = $( GRLIB ) /boards/ $( BOARD ) /default.ut
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CLEAN = soft-clean
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TECHLIBS = proasic3
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip hynix ihp gleichmann micron usbhc
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DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
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pci grusbhc haps slink ascs pwm coremp7 spi ac97
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FILESKIP = i2cmst.vhd
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#TECHLIBS = unisim
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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my-clean : clean
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-rm -rf *~
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################## project specific targets ##########################
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designs/Projet-LeonLFR-A3P3K-Sheldon/Makefile
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EFFORT=high
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XSTOPT =
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XSTOPT =
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SYNPOPT = "set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
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SYNPOPT = "set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
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VHDLSYNFILES = config.vhd ahbrom.vhd leon3mp.vhd
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VHDLSYNFILES = config.vhd ahbrom.vhd leon3mp.vhd
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VHDLSIMFILES = testbench.vhd
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VHDLSIMFILES = testbench.vhd
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SIMTOP = testbench
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SIMTOP = testbench
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SDCFILE = $( GRLIB ) /boards/ $( BOARD ) /synplify.sdc
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SDCFILE = $( GRLIB ) /boards/ $( BOARD ) /synplify.sdc
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SDC = $( GRLIB ) /boards/ $( BOARD ) /leon3mp.sdc
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SDC = $( GRLIB ) /boards/ $( BOARD ) /leon3mp.sdc
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lib/lpp/lpp_dma/lpp_dma_ip.vhd
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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