HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Projet-LeonLFR-A3PE3kL-Sheldon-DataFlux/synthesis/leon3mp.srl

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# Created by Synplify VHDL Compiler version comp520rcp1, Build 028R from Synplicity, Inc.

# Synthesis Netlist written on Thu Dec 19 12:48:58 2013

#

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f "C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.vhd"; # file 24

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\actar.vhd"; # file 25

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd"; # file 26

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd"; # file 27

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd"; # file 28

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\DriveInputs.vhd"; # file 29

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\GetResult.vhd"; # file 30

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Dispatch.vhd"; # file 31

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\Clock_Divider.vhd"; # file 32

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\ClkSetting.vhd"; # file 33

af .is_vhdl 1;

f "C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\arith.vhd"; # file 34

af .is_vhdl 1;

f "C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\unsigned.vhd"; # file 35

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Gene_SYNC.vhd"; # file 36

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\Serialize.vhd"; # file 37

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\BaudGen.vhd"; # file 38

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\Shift_REG.vhd"; # file 39

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\rstgen.vhd"; # file 40

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cpu_disasx.vhd"; # file 41

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\sparc\sparc.vhd"; # file 42

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\arith\arith.vhd"; # file 43

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\modgen\leaves.vhd"; # file 44

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\modgen\multlib.vhd"; # file 45

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\allmul.vhd"; # file 46

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\stdlib\stdlib.vhd"; # file 47

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\amba.vhd"; # file 48

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\devices.vhd"; # file 49

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd"; # file 50

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_ad_Conv\AD7688_drvr.vhd"; # file 51

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\gencomp\gencomp.vhd"; # file 52

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\allclkgen.vhd"; # file 53

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\grgates.vhd"; # file 54

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\memory_inferred.vhd"; # file 55

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_2p.vhd"; # file 56

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\iir_filter.vhd"; # file 57

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd"; # file 58

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MUXN.vhd"; # file 59

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\MAC.vhd"; # file 60

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\ALU.vhd"; # file 61

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd"; # file 62

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd"; # file 63

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd"; # file 64

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd"; # file 65

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_amba\lpp_amba.vhd"; # file 66

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\misc.vhd"; # file 67

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\memctrl\memctrl.vhd"; # file 68

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_memory.vhd"; # file 69

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd"; # file 70

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_top_lfr\lpp_top_acq.vhd"; # file 71

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lpp_FIFO.vhd"; # file 72

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\lppFIFOxN.vhd"; # file 73

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftSm.vhd"; # file 75

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\fftDp.vhd"; # file 76

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\twiddle.vhd"; # file 77

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd"; # file 78

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd"; # file 79

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\dsp\lpp_fft\FFT.vhd"; # file 80

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\ALU_Driver.vhd"; # file 81

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\lpp_matrix.vhd"; # file 82

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\Matrix.vhd"; # file 83

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd"; # file 84

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd"; # file 85

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_amba\apb_devices_list.vhd"; # file 86

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\APB_FIFO.vhd"; # file 87

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\lpp_cna.vhd"; # file 88

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\DacDriver.vhd"; # file 89

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_cna\APB_DAC.vhd"; # file 90

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\lpp_uart.vhd"; # file 91

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\UART.vhd"; # file 92

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_uart\APB_UART.vhd"; # file 93

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\allpads.vhd"; # file 94

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkpad.vhd"; # file 95

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd"; # file 96

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkgen.vhd"; # file 97

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3.vhd"; # file 98

af .is_vhdl 1;

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af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\libiu.vhd"; # file 100

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\sparc\sparc_disas.vhd"; # file 101

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\iu3.vhd"; # file 102

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\inferred\mul_inferred.vhd"; # file 103

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\techmult.vhd"; # file 104

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\arith\mul32.vhd"; # file 105

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\arith\div32.vhd"; # file 106

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmuiface.vhd"; # file 107

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\libcache.vhd"; # file 108

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_icache.vhd"; # file 109

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\libmmu.vhd"; # file 110

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_dcache.vhd"; # file 111

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_acache.vhd"; # file 112

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmutlbcam.vhd"; # file 113

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f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmulrue.vhd"; # file 114

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmulru.vhd"; # file 115

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram.vhd"; # file 116

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmutlb.vhd"; # file 117

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmutw.vhd"; # file 118

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu.vhd"; # file 119

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mmu_cache.vhd"; # file 120

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\proc3.vhd"; # file 121

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram_dp.vhd"; # file 122

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\cachemem.vhd"; # file 123

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\syncram64.vhd"; # file 124

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\tbufmem.vhd"; # file 125

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\grfpw_net.vhd"; # file 126

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\regfile_3p.vhd"; # file 127

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\gencomp\netcomp.vhd"; # file 128

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\grfpwx.vhd"; # file 129

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\mfpwx.vhd"; # file 130

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\grlfpw_net.vhd"; # file 131

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\grlfpwx.vhd"; # file 132

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\libproc3.vhd"; # file 133

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\leon3s.vhd"; # file 134

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\outpad.vhd"; # file 135

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\clkand.vhd"; # file 136

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3x.vhd"; # file 137

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\dsu3.vhd"; # file 138

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\inpad.vhd"; # file 139

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\leon3\irqmp.vhd"; # file 140

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\memctrl\sdmctrl.vhd"; # file 141

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\memoryctrl.vhd"; # file 142

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\esa\memoryctrl\mctrl.vhd"; # file 143

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\techmap\maps\iopad.vhd"; # file 144

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_memory\SSRAM_plugin.vhd"; # file 145

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\ahbctrl.vhd"; # file 146

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\ahbmst.vhd"; # file 147

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\uart.vhd"; # file 148

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\libdcom.vhd"; # file 149

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom_uart.vhd"; # file 150

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\dcom.vhd"; # file 151

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\ahbuart.vhd"; # file 152

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\apbctrl.vhd"; # file 153

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\gptimer.vhd"; # file 154

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\uart\apbuart.vhd"; # file 155

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\gaisler\misc\grgpio.vhd"; # file 156

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\config.vhd"; # file 157

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\general_purpose\lpp_delay\lpp_delay.vhd"; # file 158

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_demux\lpp_demux.vhd"; # file 159

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_Header\lpp_Header.vhd"; # file 160

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\amba\dma2ahb_pkg.vhd"; # file 161

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\..\..\VHD_Lib\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd"; # file 162

af .is_vhdl 1;

f "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd"; # file 163

af .is_vhdl 1;

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