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r398:51d54eefa77b JC
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@@ -138,6 +138,9 ARCHITECTURE beh OF LFR_em IS
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
141
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
143
141 BEGIN -- beh
144 BEGIN -- beh
142
145
143 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
@@ -371,6 +374,8 BEGIN -- beh
371 coarse_time => coarse_time,
374 coarse_time => coarse_time,
372 fine_time => fine_time,
375 fine_time => fine_time,
373 data_shaping_BW => bias_fail_sw,
376 data_shaping_BW => bias_fail_sw,
377 observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
374 observation_reg => observation_reg);
379 observation_reg => observation_reg);
375
380
376
381
@@ -389,14 +394,16 BEGIN -- beh
389 PORT MAP (
394 PORT MAP (
390 cnv_clk => clk_24, -- TODO : 49.152
395 cnv_clk => clk_24, -- TODO : 49.152
391 cnv_rstn => rstn, -- ok
396 cnv_rstn => rstn, -- ok
392 cnv => ADC_smpclk, -- ok
397 cnv => ADC_smpclk_s, -- ok
393 clk => clk_25, -- ok
398 clk => clk_25, -- ok
394 rstn => rstn, -- ok
399 rstn => rstn, -- ok
395 ADC_data => ADC_data, -- ok
400 ADC_data => ADC_data, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
401 ADC_nOE => ADC_OEB_bar_CH, -- ok
397 sample => sample, -- ok
402 sample => sample, -- ok
398 sample_val => sample_val); -- ok
403 sample_val => sample_val); -- ok
399
404
400 TAG8 <= ADC_smpclk;
405 ADC_smpclk <= ADC_smpclk_s;
406
407 TAG8 <= ADC_smpclk_s;
401
408
402 END beh;
409 END beh;
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