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#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010
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#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1
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#OS: 6.1
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#Hostname: PC-SOLAR2
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#Implementation: synthesis
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#Thu Dec 19 12:30:25 2013
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$ Start of Compile
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#Thu Dec 19 12:30:25 2013
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Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
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@N|Running in 32-bit mode
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Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
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@N: CD720 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":50:7:50:13|Top entity is set to leon3mp.
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@W: CD433 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\..\..\lib\grlib\sparc\sparc_disas.vhd":720:24:720:24|No design units in file
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@W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":266:15:266:22|dac_sclk is not readable. This may cause a simulation mismatch.
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@W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":267:15:267:22|dac_data is not readable. This may cause a simulation mismatch.
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@W: CD266 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":268:15:268:22|dac_sync is not readable. This may cause a simulation mismatch.
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@E: CD213 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":272:11:272:21|Undefined identifier
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@E: CD415 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd":458:8:458:14|Expecting keyword is
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2 errors parsing file C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-LeonLFR-A3PE3kL-Sheldon\leon3mp.vhd
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@END
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@E|Parse errors encountered - exiting
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Process took 0h:00m:02s realtime, 0h:00m:01s cputime
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# Thu Dec 19 12:30:27 2013
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###########################################################]
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