HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/general_purpose/MUX2.vhd

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

Alexis - - Load All Authors

File last commit:

r38:3488e1e84506 default


                r655:2dbcdaf8bb73

default

Download file

             MUX2.vhd
        
                    49 lines
            
             | 1.7 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / general_purpose / MUX2.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

      --                    Author : Alexis Jeandet

      --                     Mail : alexis.jeandet@lpp.polytechnique.fr

      ----------------------------------------------------------------------------

      library IEEE;

      use IEEE.numeric_std.all;

      use IEEE.std_logic_1164.all;

      library lpp;

      use lpp.general_purpose.all;

      entity MUX2 is 

      generic(Input_SZ     :   integer := 16);

      port(

          sel     :   in  std_logic;

          IN1     :   in  std_logic_vector(Input_SZ-1 downto 0);

          IN2     :   in  std_logic_vector(Input_SZ-1 downto 0);

          RES     :   out std_logic_vector(Input_SZ-1 downto 0)

      );

      end entity;

      architecture ar_MUX2 of MUX2 is

      begin

      RES     <=  IN1 when sel = '0' else IN2;

      end ar_MUX2;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				------------------------------------------------------------------------------
				-- This file is a part of the LPP VHDL IP LIBRARY
				-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
				--
				-- This program is free software; you can redistribute it and/or modify
				-- it under the terms of the GNU General Public License as published by
				-- the Free Software Foundation; either version 3 of the License, or
				-- (at your option) any later version.
				--
				-- This program is distributed in the hope that it will be useful,
				-- but WITHOUT ANY WARRANTY; without even the implied warranty of
				-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				-- GNU General Public License for more details.
				--
				-- You should have received a copy of the GNU General Public License
				-- along with this program; if not, write to the Free Software
				-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
				-------------------------------------------------------------------------------
				-- Author : Alexis Jeandet
				-- Mail : alexis.jeandet@lpp.polytechnique.fr
				----------------------------------------------------------------------------
				library IEEE;
				use IEEE.numeric_std.all;
				use IEEE.std_logic_1164.all;
				library lpp;
				use lpp.general_purpose.all;



				entity MUX2 is
				generic(Input_SZ : integer := 16);
				port(
				sel : in std_logic;
				IN1 : in std_logic_vector(Input_SZ-1 downto 0);
				IN2 : in std_logic_vector(Input_SZ-1 downto 0);
				RES : out std_logic_vector(Input_SZ-1 downto 0)
				);
				end entity;




				architecture ar_MUX2 of MUX2 is

				begin

				RES <= IN1 when sel = '0' else IN2;

				end ar_MUX2;