##// END OF EJS Templates
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

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Makefile_RTAX.inc
41 lines | 733 B | text/x-povray | PovrayLexer
PACKAGE=CQFP352
SPEED=Std
SYNFREQ=50
TECHNOLOGY=Axcelerator
DESIGNER_PACKAGE=CQFP
DESIGNER_PINS=352
DESIGNER_VOLTAGE=COM
DESIGNER_TEMP=COM
#ifeq ("$(FPGA_RTAX4000)","S")
# LIBERO_DIE=70800rts
# PART=RTAX4000S
# LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
#endif
#ifeq ("$(FPGA_RTAX4000)","D")
LIBERO_DIE=70800d
PART=RTAX4000D
LIBERO_PACKAGE=cq$(DESIGNER_PINS)
#endif
MANUFACTURER=Actel
MGCPART=$(PART)
MGCTECHNOLOGY=Axcelerator
MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
## RTAX4000S OPTIONS
#LIBERO_DIE=70800rts
#PART=RTAX4000S
## RTAX4000D OPTIONS
#LIBERO_DIE=70800d
#PART=RTAX4000D
# RTAX4000D
#LIBERO_PACKAGE=cq$(DESIGNER_PINS)
# RTAX4000S
#LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r