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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.
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r612:f5ec87dbbcce simu_with_Leon3
r655:2dbcdaf8bb73 default
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LFR_EQM_altran_syn.sdc
50 lines | 890 B | application/vnd.stardivision.calc | TextLexer
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# Synopsys, Inc. constraint file
# E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc
# Written on Fri Jun 12 10:24:30 2015
# by Synplify Pro, E-2010.09A-1 Scope Editor
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# Collections
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# Clocks
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define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
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# Delay Paths
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# Attributes
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# I/O Standards
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# Other
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