##// END OF EJS Templates
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

File last commit:

r181:2a5b3fda6e52 alexis
r655:2dbcdaf8bb73 default
Show More
Makefile.inc
18 lines | 318 B | text/x-povray | MakefileLexer
TECHNOLOGY=PROASIC3
PACKAGE=\"\"
SPEED=Std
SYNFREQ=50
PART=A3PE3000L
DESIGNER_PACKAGE=FBGA
DESIGNER_PINS=324
DESIGNER_VOLTAGE=COM
DESIGNER_TEMP=COM
MANUFACTURER=Actel
MGCPART=$(PART)
MGCTECHNOLOGY=PROASIC3
MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
LIBERO_DIE=IT14X14M4LDP
LIBERO_PACKAGE=fg$(DESIGNER_PINS)