HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_FIFO_Shared/run_with_head_reg_lantency_1.do

LFR-EQM 2.1.82 - b...

LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------|___________ CLK_25Mhz-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_| ADC_OEn ------------|___|----- ADC_DATA ****************{data} ADC_DATA_reg****************{data}

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             run_with_head_reg_lantency_1.do
        
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      vcom -quiet  -93  -work work tb_with_head_reg_latency_1.vhd

      vsim work.testbench

      log -r *

      do wave_head_reg_latency_1.do

      run -all

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				vcom -quiet -93 -work work tb_with_head_reg_latency_1.vhd

				vsim work.testbench

				log -r *

				do wave_head_reg_latency_1.do

				run -all