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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fifo_ctrl IS
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generic(
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offset : INTEGER := 0;
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length : INTEGER := 20;
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enable_ready : STD_LOGIC := '1'
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ren : IN STD_LOGIC;
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wen : IN STD_LOGIC;
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mem_re : OUT STD_LOGIC;
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mem_we : OUT STD_LOGIC;
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mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
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mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
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ready : OUT STD_LOGIC
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS
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SIGNAL sFull : STD_LOGIC;
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SIGNAL sFull_s : STD_LOGIC;
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SIGNAL sEmpty_s : STD_LOGIC;
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SIGNAL sEmpty : STD_LOGIC;
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SIGNAL sREN : STD_LOGIC;
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SIGNAL sWEN : STD_LOGIC;
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SIGNAL sRE : STD_LOGIC;
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SIGNAL sWE : STD_LOGIC;
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SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
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SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
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SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
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SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
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BEGIN
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mem_re <= sRE;
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mem_we <= sWE;
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--=============================
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-- Read section
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--=============================
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sREN <= REN OR sEmpty;
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sRE <= NOT sREN;
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sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
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'1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
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'0';
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Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')then
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Raddr_vect <= 0;
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sempty <= '1';
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ELSIF(clk'EVENT AND clk = '1')then
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sEmpty <= sempty_s;
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IF(sREN = '0' and sempty = '0')then
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Raddr_vect <= Raddr_vect_s;
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END IF;
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END IF;
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END PROCESS;
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--=============================
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-- Write section
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--=============================
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sWEN <= WEN OR sFull;
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sWE <= NOT sWEN;
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sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
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'1' WHEN sFull = '1' AND REN = '1' ELSE
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'0';
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Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')then
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Waddr_vect <= 0;
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sfull <= '0';
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ELSIF(clk'EVENT AND clk = '1')then
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sfull <= sfull_s;
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IF(sWEN = '0' and sfull = '0')THEN
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Waddr_vect <= Waddr_vect_s;
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END IF;
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END IF;
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END PROCESS;
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mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
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mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
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ready_gen: IF enable_ready = '1' GENERATE
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ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
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'1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
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'0';
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END GENERATE ready_gen;
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ready_not_gen: IF enable_ready = '0' GENERATE
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ready <= '0';
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END GENERATE ready_not_gen;
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END ARCHITECTURE;
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