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include .config
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#GRLIB=../..
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TOP=leon3mp
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BOARD=xilinx-sp605-xc6slx45t
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include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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DEVICE=$(PART)-$(PACKAGE)$(SPEED)
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#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
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UCF=leon3mp.ucf
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QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
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EFFORT=high
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ISEMAPOPT="-timing"
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XSTOPT=""
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SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
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VHDLOPTSYNFILES= mig/mig_38/user_design/rtl/iodrp_controller.vhd \
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mig/mig_38/user_design/rtl/iodrp_mcb_controller.vhd \
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mig/mig_38/user_design/rtl/mcb_raw_wrapper.vhd \
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mig/mig_38/user_design/rtl/mcb_soft_calibration.vhd \
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mig/mig_38/user_design/rtl/mcb_soft_calibration_top.vhd \
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mig/mig_38/user_design/rtl/memc3_infrastructure.vhd \
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mig/mig_38/user_design/rtl/memc3_wrapper.vhd \
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mig/mig_38/user_design/rtl/mig_38.vhd
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VHDLSYNFILES= \
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config.vhd svga2ch7301c.vhd ahbrom.vhd \
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ahb2mig_sp605.vhd vga_clkgen.vhd leon3mp.vhd
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VHDLSIMFILES=testbench.vhd
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SIMTOP=testbench
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#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
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SDCFILE=default.sdc
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BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
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CLEAN=soft-clean
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VCOMOPT=-explicit
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TECHLIBS = secureip unisim
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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip cypress ihp gleichmann gsi fmf spansion
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DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
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leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
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ac97 hcan usb
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DIRADD = leon3ftv2
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FILEADD = MCB.vhd
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FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
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include $(GRLIB)/bin/Makefile
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include $(GRLIB)/software/leon3/Makefile
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################## project specific targets ##########################
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mig:
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coregen -b mig/mig.xco -p mig
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patch -p0 < mig.diff
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migclean:
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-rm -rf mig/mig_38* mig/tmp
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.PHONY: mig
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