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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.chirp_pkg.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL clk_24k : STD_LOGIC := '0';
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SIGNAL clk_24k_r : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL run : STD_LOGIC;
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SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
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SIGNAL data_in_valid : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT CARRY : STD_LOGIC := '1';
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CONSTANT CARRY_NO : STD_LOGIC := '0';
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CONSTANT ADD : STD_LOGIC := '0';
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CONSTANT SUB : STD_LOGIC := '1';
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SIGNAL OP : STD_LOGIC;
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SIGNAL OP_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL OP_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL data_out_verif : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_verif_s : STD_LOGIC_VECTOR(32 DOWNTO 0);
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SIGNAL data_in_A_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_in_B_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_in_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_in_B : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_diff : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_Carry : STD_LOGIC;
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SIGNAL COUNTER_A : INTEGER;
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SIGNAL COUNTER_B : INTEGER;
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CONSTANT COUNTER_MIN : INTEGER := INTEGER'LOW;
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CONSTANT COUNTER_MAX : INTEGER := INTEGER'HIGH;
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CONSTANT COUNTER_STEP : INTEGER := INTEGER'HIGH/100;
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SIGNAL ALL_is_OK : STD_LOGIC;
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BEGIN
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clk <= NOT clk AFTER 5 ns;
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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run <= '0';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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run <= '1';
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WAIT UNTIL clk = '1';
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OP <= ADD;
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WAIT FOR 500 us;
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OP <= SUB;
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WAIT FOR 500 us;
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REPORT "*** END simulation ***" SEVERITY failure;
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WAIT;
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END PROCESS;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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COUNTER_A <= COUNTER_MIN;
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COUNTER_B <= COUNTER_MIN;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF COUNTER_A < COUNTER_MAX - COUNTER_STEP THEN
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COUNTER_A <= COUNTER_A + COUNTER_STEP;
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ELSE
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COUNTER_A <= COUNTER_MIN;
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IF COUNTER_B < COUNTER_MAX - COUNTER_STEP THEN
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COUNTER_B <= COUNTER_B + COUNTER_STEP;
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ELSE
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COUNTER_B <= COUNTER_MIN;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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data_in_A <= STD_LOGIC_VECTOR(to_signed(COUNTER_A,32));
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data_in_B <= STD_LOGIC_VECTOR(to_signed(COUNTER_B,32));
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-----------------------------------------------------------------------------
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OP_0 <= CARRY_NO & OP;
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OP_1 <= CARRY & OP;
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cic_lfr_add_sub_1: cic_lfr_add_sub
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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OP => OP_0,
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data_in_A => data_in_A(15 DOWNTO 0),
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data_in_B => data_in_B(15 DOWNTO 0),
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data_in_Carry => '0',
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data_out => data_out_s,
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data_out_Carry => data_out_Carry);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_in_A_reg <= (OTHERS => '0');
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data_in_B_reg <= (OTHERS => '0');
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data_out(15 DOWNTO 0) <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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data_in_A_reg <= data_in_A;
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data_in_B_reg <= data_in_B;
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data_out(15 DOWNTO 0) <= data_out_s;
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END IF;
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END PROCESS;
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cic_lfr_add_sub_2: cic_lfr_add_sub
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PORT MAP (
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clk => clk,
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rstn => rstn,
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run => run,
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OP => OP_1,
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data_in_A => data_in_A_reg(31 DOWNTO 16),
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data_in_B => data_in_B_reg(31 DOWNTO 16),
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data_in_Carry => data_out_Carry,
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data_out => data_out(31 DOWNTO 16),
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data_out_Carry => OPEN);
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-----------------------------------------------------------------------------
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data_out_verif_s <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) + to_integer(SIGNED(data_in_B_reg)),33)) WHEN OP = ADD ELSE
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STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) - to_integer(SIGNED(data_in_B_reg)),33));
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_out_verif <= (OTHERS => '0');
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ALL_is_OK <= '0';
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data_out_pre <= (OTHERS => '0');
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data_out_diff <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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data_out_verif <= data_out_verif_s(31 DOWNTO 0);
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IF data_out_verif = data_out THEN
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ALL_is_OK <= '1';
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ELSE
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ALL_is_OK <= '0';
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END IF;
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-------------------------------------------------------------------------
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data_out_pre <= data_out;
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IF OP = ADD THEN
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data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32));
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ELSE
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data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32));
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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END;
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