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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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--LIBRARY lpp;
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--USE lpp.iir_filter.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY TB IS
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END TB;
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ARCHITECTURE beh OF TB IS
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COMPONENT RAM_CEL
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GENERIC (
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DataSz : integer range 1 to 32;
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abits : integer range 2 to 12);
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PORT (
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WD : in std_logic_vector(DataSz-1 downto 0);
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RD : out std_logic_vector(DataSz-1 downto 0);
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WEN, REN : in std_logic;
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WADDR : in std_logic_vector(abits-1 downto 0);
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RADDR : in std_logic_vector(abits-1 downto 0);
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RWCLK, RESET : in std_logic);
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END COMPONENT;
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CONSTANT DATA_SIZE : INTEGER := 8;
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CONSTANT ADDR_BIT_NUMBER : INTEGER := 8;
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-----------------------------------------------------------------------------
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL write_data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
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SIGNAL write_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
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SIGNAL write_enable : STD_LOGIC;
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SIGNAL write_enable_n : STD_LOGIC;
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SIGNAL read_data_ram : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
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SIGNAL read_data_cel : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
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SIGNAL read_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
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SIGNAL read_enable : STD_LOGIC;
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SIGNAL read_enable_n : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT RANDOM_VECTOR_SIZE : INTEGER := DATA_SIZE + ADDR_BIT_NUMBER + ADDR_BIT_NUMBER + 2;
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CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : real := (2**RANDOM_VECTOR_SIZE)*1.0;
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SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL error_value : STD_LOGIC;
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SIGNAL warning_value : STD_LOGIC;
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SIGNAL warning_value_clocked : STD_LOGIC;
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CONSTANT READ_DATA_ALL_X : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'X');
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CONSTANT READ_DATA_ALL_U : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'U');
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CONSTANT READ_DATA_ALL_0 : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => '0');
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BEGIN -- beh
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clk <= NOT clk AFTER 10 ns;
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rstn <= '1' AFTER 30 ns;
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-----------------------------------------------------------------------------
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CEL: RAM_CEL
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GENERIC MAP (
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DataSz => DATA_SIZE,
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abits => ADDR_BIT_NUMBER)
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PORT MAP (
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WD => write_data,
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RD => read_data_cel,
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WEN => write_enable_n,
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REN => read_enable_n,
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WADDR => write_addr,
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RADDR => read_addr,
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RWCLK => clk,
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RESET => rstn);
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RAM : syncram_2p
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GENERIC MAP(tech => 0, abits => ADDR_BIT_NUMBER, dbits => DATA_SIZE)
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PORT MAP(rclk => clk, renable => read_enable, raddress => read_addr, dataout => read_data_ram,
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wclk => clk, write => write_enable, waddress => write_addr, datain => write_data);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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VARIABLE seed1, seed2 : POSITIVE;
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VARIABLE rand1 : REAL;
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VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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random_vector <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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UNIFORM(seed1,seed2,rand1);
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RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
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to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
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RANDOM_VECTOR_VAR'LENGTH)
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);
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random_vector <= RANDOM_VECTOR_VAR ;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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write_data <= random_vector(DATA_SIZE-1 DOWNTO 0);
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write_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE);
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read_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE+ADDR_BIT_NUMBER);
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read_enable <= random_vector(RANDOM_VECTOR_SIZE-2);
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write_enable <= random_vector(RANDOM_VECTOR_SIZE-1);
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read_enable_n <= NOT read_enable;
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write_enable_n <= NOT write_enable;
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-----------------------------------------------------------------------------
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warning_value <= '0' WHEN read_data_ram = read_data_cel ELSE
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'1';
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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error_value <= '0';
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warning_value_clocked <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF read_data_ram = read_data_cel THEN
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error_value <= '0';
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warning_value_clocked <= '0';
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ELSE
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warning_value_clocked <= '1';
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IF read_data_ram = READ_DATA_ALL_U AND read_data_cel = READ_DATA_ALL_0 THEN
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error_value <= '0';
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ELSE
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error_value <= '1';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END beh;
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