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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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USE lpp.chirp_pkg.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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CONSTANT VECTOR_SIZE : INTEGER := 4*2;
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SIGNAL VECTOR_1 : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL VECTOR_MIN : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL VECTOR_MAX : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL all_done : STD_LOGIC;
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SIGNAL all_ok : STD_LOGIC;
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SIGNAL all_ok_E : STD_LOGIC;
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SIGNAL A : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL C : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL D_0 : STD_LOGIC_VECTOR(VECTOR_SIZE/2 DOWNTO 0);
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SIGNAL D_1 : STD_LOGIC_VECTOR(VECTOR_SIZE/2-1 DOWNTO 0);
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SIGNAL D : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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SIGNAL E : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
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BEGIN
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VECTOR_1(0) <= '1';
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VECTOR_1(VECTOR_SIZE-1 DOWNTO 1) <= (OTHERS => '0') ;
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VECTOR_MIN(VECTOR_SIZE-1) <= '1';
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VECTOR_MIN(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '0') ;
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VECTOR_MAX(VECTOR_SIZE-1) <= '0';
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VECTOR_MAX(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '1') ;
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clk <= NOT clk AFTER 5 ns;
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PROCESSD_0(VECTOR_SIZE/2)
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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rstn <= '0';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL clk = '1';
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WAIT FOR 2 ms;
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REPORT "*** END simulation ***" SEVERITY failure;
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WAIT;
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END PROCESS;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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A <= VECTOR_MIN;
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B <= VECTOR_MIN;
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all_done <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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all_done <= '0';
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IF A = VECTOR_MAX THEN
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A <= VECTOR_MIN;
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IF B = VECTOR_MAX THEN
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B <= VECTOR_MIN;
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all_done <= '1';
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ELSE
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B <= STD_LOGIC_VECTOR(signed(B) + signed(VECTOR_1));
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END IF;
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ELSE
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A <= STD_LOGIC_VECTOR(signed(A) + signed(VECTOR_1));
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END IF;
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END IF;
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END PROCESS;
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C <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
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E <= STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B));
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D_0 <= STD_LOGIC_VECTOR(SIGNED('0'&A(VECTOR_SIZE/2-1 DOWNTO 0)) - SIGNED('0' & B(VECTOR_SIZE/2-1 DOWNTO 0)));
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D_1 <= STD_LOGIC_VECTOR( SIGNED(A(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2))
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- SIGNED(B(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2))
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- SIGNED(VECTOR_1(VECTOR_SIZE/2-1 DOWNTO 1) & D_0(VECTOR_SIZE/2) ));
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D <= D_1(VECTOR_SIZE/2-1 DOWNTO 0) & D_0(VECTOR_SIZE/2-1 DOWNTO 0);
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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all_ok <= '1';
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all_ok_E <= '1';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF D = C THEN
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all_ok <= '1';
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ELSE
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all_ok <= '0';
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END IF;
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IF E = C THEN
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all_ok_E <= '1';
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ELSE
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all_ok_E <= '0';
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END IF;
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END IF;
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END PROCESS;
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END;
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