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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_lfr_filter_coeff.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY IIR_CEL_TEST_v3 IS
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sample_in1_val : IN STD_LOGIC;
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sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_in2_val : IN STD_LOGIC;
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sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_out1_val : OUT STD_LOGIC;
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sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0);
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sample_out2_val : OUT STD_LOGIC;
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sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)
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);
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END IIR_CEL_TEST_v3;
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ARCHITECTURE beh OF IIR_CEL_TEST_v3 IS
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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CONSTANT CEL_NUMBER : INTEGER := 5;
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CONSTANT COEFFICIENT_SIZE : INTEGER := 9;
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CONSTANT POINT_POSITION : INTEGER := 7;
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CONSTANT COEFFICIENT_PER_CEL : INTEGER := 5;
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SIGNAL coeff_test : STD_LOGIC_VECTOR((CEL_NUMBER * 5 * COEFFICIENT_SIZE)-1 DOWNTO 0);
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SIGNAL f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
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(
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(1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
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(1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
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(1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
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(1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
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(1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
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);
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SIGNAL f0_to_f1_gain : COEFF_CEL_REAL :=
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( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
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SUBTYPE COEFFICIENT IS STD_LOGIC_VECTOR(COEFFICIENT_SIZE-1 DOWNTO 0);
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TYPE COEFFICIENT_CEL IS ARRAY (1 TO 5) OF COEFFICIENT;
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TYPE COEFFICIENT_GLOBAL IS ARRAY (INTEGER RANGE <>) OF COEFFICIENT_CEL;
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SIGNAL coeff_test_2 : COEFFICIENT_GLOBAL(1 TO 5);
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-----------------------------------------------------------------------------
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SIGNAL f_to_f0_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
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(
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(1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
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(1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
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(1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
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(1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
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(1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
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);
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SIGNAL f_to_f0_gain : COEFF_CEL_REAL :=
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( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
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BEGIN -- beh
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coeff_test <=
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get_IIR_CEL_FILTER_CONFIG(
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COEFFICIENT_SIZE, POINT_POSITION, CEL_NUMBER,
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f0_to_f1_sos, f0_to_f1_gain);
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all_cel: FOR I IN 0 TO 4 GENERATE
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all_coeff: FOR J IN 0 TO 4 GENERATE
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coeff_test_2(I+1)(J+1) <=
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coeff_test((I*5+J+1)*COEFFICIENT_SIZE-1 DOWNTO (I*5+J)*COEFFICIENT_SIZE);
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END GENERATE all_coeff;
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END GENERATE all_cel;
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coefs_v2 <= CoefsInitValCst_v2;
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--IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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-- GENERIC MAP (
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-- tech => 0,
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-- Mem_use => use_CEL, -- use_RAM
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-- Sample_SZ => 18,
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-- Coef_SZ => Coef_SZ,
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-- Coef_Nb => 25,
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-- Coef_sel_SZ => 5,
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-- Cels_count => Cels_count,
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-- ChanelsCount => ChanelCount)
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-- PORT MAP (
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-- rstn => rstn,
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-- clk => clk,
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-- virg_pos => 7,
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-- coefs => coefs_v2,
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-- sample_in_val => sample_in_val,
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-- sample_in => sample_in,
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-- sample_out_val => sample_out_val,
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-- sample_out => sample_out);
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IIR_CEL_CTRLR_v3_1: IIR_CEL_CTRLR_v3
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GENERIC MAP (
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tech => 0,
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Mem_use => use_CEL,
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25,
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Coef_sel_SZ => 5,
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => coefs_v2,
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sample_in1_val => sample_in1_val,
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sample_in1 => sample_in1,
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sample_in2_val => sample_in2_val,
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sample_in2 => sample_in2,
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sample_out1_val => sample_out1_val,
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sample_out1 => sample_out1,
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sample_out2_val => sample_out2_val,
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sample_out2 => sample_out2);
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END beh;
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