HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r423:fe8f46873298

Update AD CONV for RHF1401 (LFR-EM) with filter

pellion -

r423:fe8f46873298 JC

parent child

Context file:

r423:fe8f46873298

Collapse all files

lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +4 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             PACKAGE lpp_ad_conv IS
               --CONSTANT AD7688  : INTEGER := 0;
               --CONSTANT ADS7886 : INTEGER := 1;
               --TYPE AD7688_out IS
               --RECORD
               --  CNV : STD_LOGIC;
               --  SCK : STD_LOGIC;
               --END RECORD;
               --TYPE AD7688_in_element IS
               --RECORD
               --  SDI : STD_LOGIC;
               --END RECORD;
               --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
               TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
               SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
               SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
               SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
               SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
               SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
               SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
               TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
               TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
+              TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
               TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
               TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
               TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
               TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
               COMPONENT AD7688_drvr
                 GENERIC (
                   ChanelCount     : INTEGER;
                   ncycle_cnv_high : INTEGER := 79;
                   ncycle_cnv      : INTEGER := 500);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv_run    : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   sck        : OUT STD_LOGIC;
                   sdo        : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT RHF1401_drvr IS
                 GENERIC(
                   ChanelCount : INTEGER := 8);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   ADC_data   : IN  Samples14;
                   --ADC_smpclk : OUT STD_LOGIC;
                   ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT top_ad_conv_RHF1401
                 GENERIC (
                   ChanelCount : INTEGER;
                   ncycle_cnv_high : INTEGER := 79;
                   ncycle_cnv      : INTEGER := 500);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   ADC_data   : IN  Samples14;
                   ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT AD7688_drvr_sync
                 GENERIC (
                   ChanelCount     : INTEGER;
                   ncycle_cnv_high : INTEGER;
                   ncycle_cnv      : INTEGER);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv_run    : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   sck        : OUT STD_LOGIC;
                   sdo        : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT TestModule_RHF1401
                 GENERIC (
                   freq      : INTEGER;
                   amplitude : INTEGER;
                   impulsion : INTEGER);
                 PORT (
                   ADC_smpclk  : IN  STD_LOGIC;
                   ADC_OEB_bar : IN  STD_LOGIC;
                   ADC_data    : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
               END COMPONENT;
               --COMPONENT AD7688_drvr IS
               --  GENERIC(ChanelCount : INTEGER;
               --          clkkHz      : INTEGER);
               --  PORT (clk        : IN  STD_LOGIC;
               --         rstn      : IN  STD_LOGIC;
               --         enable    : IN  STD_LOGIC;
               --         smplClk   : IN  STD_LOGIC;
               --         DataReady : OUT STD_LOGIC;
               --         smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
               --         AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --         AD_out    : OUT AD7688_out);
               --END COMPONENT;
               --COMPONENT AD7688_spi_if IS
               --  GENERIC(ChanelCount : INTEGER);
               --  PORT(clk           : IN  STD_LOGIC;
               --           reset     : IN  STD_LOGIC;
               --           cnv       : IN  STD_LOGIC;
               --           DataReady : OUT STD_LOGIC;
               --           sdi       : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --           smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0)
               --           );
               --END COMPONENT;
               --COMPONENT lpp_apb_ad_conv
               --  GENERIC(
               --    pindex      : INTEGER := 0;
               --    paddr       : INTEGER := 0;
               --    pmask       : INTEGER := 16#fff#;
               --    pirq        : INTEGER := 0;
               --    abits       : INTEGER := 8;
               --    ChanelCount : INTEGER := 1;
               --    clkkHz      : INTEGER := 50000;
               --    smpClkHz    : INTEGER := 100;
               --    ADCref      : INTEGER := AD7688);
               --  PORT (
               --    clk    : IN  STD_LOGIC;
               --    reset  : IN  STD_LOGIC;
               --    apbi   : IN  apb_slv_in_type;
               --    apbo   : OUT apb_slv_out_type;
               --    AD_in  : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --    AD_out : OUT AD7688_out);
               --END COMPONENT;
               --COMPONENT ADS7886_drvr IS
               --  GENERIC(ChanelCount : INTEGER;
               --          clkkHz      : INTEGER);
               --  PORT (
               --    clk       : IN  STD_LOGIC;
               --    reset     : IN  STD_LOGIC;
               --    smplClk   : IN  STD_LOGIC;
               --    DataReady : OUT STD_LOGIC;
               --    smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
               --    AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --    AD_out    : OUT AD7688_out
               --    );
               --END COMPONENT;
               --COMPONENT WriteGen_ADC IS
               --  PORT(
               --    clk       : IN  STD_LOGIC;
               --    rstn      : IN  STD_LOGIC;
               --    SmplCLK   : IN  STD_LOGIC;
               --    DataReady : IN  STD_LOGIC;
               --    Full      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
               --    ReUse     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
               --    Write     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
               --    );
               --END COMPONENT;
             --===========================================================|
             --=======================  ADS 127X =========================|
             --===========================================================|
               TYPE     ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
               CONSTANT ADS127X_SPI_FORMAT   : ADS127X_FORMAT_Type := "010";
               CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
               TYPE     ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
               CONSTANT ADS127X_MODE_low_power       : ADS127X_MODE_Type := "10";
               CONSTANT ADS127X_MODE_low_speed       : ADS127X_MODE_Type := "11";
               CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
               TYPE ADS127X_config IS
               RECORD
                 SYNC   : STD_LOGIC;
                 CLKDIV : STD_LOGIC;
                 FORMAT : ADS127X_FORMAT_Type;
                 MODE   : ADS127X_MODE_Type;
               END RECORD;
               COMPONENT ADS1274_DRIVER IS
                 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
                 PORT(
                   Clk     : IN  STD_LOGIC;
                   reset   : IN  STD_LOGIC;
                   SpiClk  : OUT STD_LOGIC;
                   DIN     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   Ready   : IN  STD_LOGIC;
                   Format  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   Mode    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   ClkDiv  : OUT STD_LOGIC;
                   PWDOWN  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   SmplClk : IN  STD_LOGIC;
                   OUT0    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT1    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT2    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT3    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   FSynch  : OUT STD_LOGIC;
                   test    : OUT STD_LOGIC
                   );
               END COMPONENT;
             -- todo clean file
               COMPONENT DUAL_ADS1278_DRIVER IS
                 PORT(
                   Clk     : IN  STD_LOGIC;
                   reset   : IN  STD_LOGIC;
                   SpiClk  : OUT STD_LOGIC;
                   DIN     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   SmplClk : IN  STD_LOGIC;
                   OUT00   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT01   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT02   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT03   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT04   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT05   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT06   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT07   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT10   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT11   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT12   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT13   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT14   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT15   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT16   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT17   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   FSynch  : OUT STD_LOGIC
                   );
               END COMPONENT;
             --===========================================================|
             -- DRIVER ADS7886
             --===========================================================|
             COMPONENT top_ad_conv_ADS7886_v2 IS
               GENERIC(
                 ChannelCount 	: INTEGER := 8;
             	SampleNbBits	: INTEGER := 14;
                 ncycle_cnv_high : INTEGER := 40;	-- at least 32 cycles
                 ncycle_cnv      : INTEGER := 500);
               PORT (
             	-- CONV
                 cnv_clk  	: IN STD_LOGIC;
                 cnv_rstn 	: IN STD_LOGIC;
                 cnv 		: OUT STD_LOGIC;
             	-- DATA
                 clk        	: IN  STD_LOGIC;
                 rstn       	: IN  STD_LOGIC;
             	sck			: OUT STD_LOGIC;
             	sdo			: IN  STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
             	-- SAMPLE
                 sample     : OUT Samples14v(ChannelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END COMPONENT;
             COMPONENT ADS7886_drvr_v2 IS
               GENERIC(
                 ChannelCount	: INTEGER	:= 8;
                 NbBitsSamples	: INTEGER	:= 16);
               PORT (
                 -- CONV --
                 cnv_clk   : IN  STD_LOGIC;
                 cnv_rstn  : IN  STD_LOGIC;
                 -- DATA --
                 clk  : IN  STD_LOGIC;
                 rstn : IN  STD_LOGIC;
                 sck  : OUT STD_LOGIC;
                 sdo  : IN  STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
             	-- SAMPLE --
                 sample     : OUT Samples(ChannelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END COMPONENT;
             COMPONENT top_ad_conv_RHF1401_withFilter
               GENERIC (
                 ChanelCount     : INTEGER;
                 ncycle_cnv_high : INTEGER;
                 ncycle_cnv      : INTEGER);
               PORT (
                 cnv_clk    : IN  STD_LOGIC;
                 cnv_rstn   : IN  STD_LOGIC;
                 cnv        : OUT STD_LOGIC;
                 clk        : IN  STD_LOGIC;
                 rstn       : IN  STD_LOGIC;
                 ADC_data   : IN  Samples14;
                 ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                 sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC);
             END COMPONENT;
             END lpp_ad_conv;

lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +10 -10

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.general_purpose.SYNC_FF;
             ENTITY top_ad_conv_RHF1401_withFilter IS
               GENERIC(
                 ChanelCount     : INTEGER := 8;
                 ncycle_cnv_high : INTEGER := 13;
                 ncycle_cnv      : INTEGER := 25);
               PORT (
                 cnv_clk  : IN STD_LOGIC;            -- 24Mhz
                 cnv_rstn : IN STD_LOGIC;
                 cnv : OUT STD_LOGIC;
                 clk        : IN  STD_LOGIC;         -- 25MHz
                 rstn       : IN  STD_LOGIC;
                 ADC_data   : IN  Samples14;
                 ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                 sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END top_ad_conv_RHF1401_withFilter;
             ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
               SIGNAL cnv_cycle_counter : INTEGER;
               SIGNAL cnv_s             : STD_LOGIC;
               SIGNAL cnv_sync          : STD_LOGIC;
               SIGNAL cnv_sync_pre          : STD_LOGIC;
               SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
               SIGNAL enable_ADC : STD_LOGIC;
               SIGNAL sample_reg  : Samples14v(ChanelCount-1 DOWNTO 0);
               SIGNAL channel_counter : INTEGER;
               CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
               SIGNAL ADC_data_selected : Samples14;
-              SIGNAL ADC_data_result   : Samples14;
+              SIGNAL ADC_data_result   : Samples15;
               SIGNAL sample_counter : INTEGER;
             BEGIN
               -----------------------------------------------------------------------------
               -- CNV GEN
               -----------------------------------------------------------------------------
               PROCESS (cnv_clk, cnv_rstn)
               BEGIN  -- PROCESS
                 IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
                   cnv_cycle_counter <= 0;
                   cnv_s             <= '0';
                 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
                   IF cnv_cycle_counter < ncycle_cnv-1 THEN
                     cnv_cycle_counter <= cnv_cycle_counter + 1;
                     IF cnv_cycle_counter < ncycle_cnv_high THEN
                       cnv_s <= '1';
                     ELSE
                       cnv_s <= '0';
                     END IF;
                   ELSE
                     cnv_s             <= '1';
                     cnv_cycle_counter <= 0;
                   END IF;
                 END IF;
               END PROCESS;
               cnv <= cnv_s;
               -----------------------------------------------------------------------------
               -- SYNC CNV
               -----------------------------------------------------------------------------
               SYNC_FF_cnv : SYNC_FF
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk    => clk,
                   rstn   => rstn,
                   A      => cnv_s,
                   A_sync => cnv_sync);
               -----------------------------------------------------------------------------
               -- DATA GEN Output Enable
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
                   cnv_sync_pre                        <= '0';
                   enable_ADC <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   cnv_sync_pre                        <= cnv_sync;
                   IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
                     enable_ADC     <= '1';
                     ADC_nOE_reg(0) <= '0';
                     ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
                   ELSE
                     enable_ADC <= NOT enable_ADC;
                     IF enable_ADC = '0' THEN
                       ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
               -----------------------------------------------------------------------------
               -- ADC READ DATA
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   channel_counter <= MAX_COUNTER;
                   sample_reg(0) <= (OTHERS => '0');
                   sample_reg(1) <= (OTHERS => '0');
                   sample_reg(2) <= (OTHERS => '0');
                   sample_reg(3) <= (OTHERS => '0');
                   sample_reg(4) <= (OTHERS => '0');
                   sample_reg(5) <= (OTHERS => '0');
                   sample_reg(6) <= (OTHERS => '0');
                   sample_reg(7) <= (OTHERS => '0');
                   sample_val     <= '0';
                   sample_counter <= 0;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
                     channel_counter <= 0;
                   ELSE
                     IF channel_counter < MAX_COUNTER THEN
                       channel_counter <= channel_counter + 1;
                     END IF;
                   END IF;
                   sample_val     <= '0';
                   CASE channel_counter IS
-                    WHEN 0*2 => sample_reg(0) <= ADC_data_result;
+                    WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 1*2 => sample_reg(1) <= ADC_data_result;
+                    WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 2*2 => sample_reg(2) <= ADC_data_result;
+                    WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 3*2 => sample_reg(3) <= ADC_data_result;
+                    WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 4*2 => sample_reg(4) <= ADC_data_result;
+                    WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 5*2 => sample_reg(5) <= ADC_data_result;
+                    WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 6*2 => sample_reg(6) <= ADC_data_result;
+                    WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1);
-                    WHEN 7*2 => sample_reg(7) <= ADC_data_result;
+                    WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1);
                       IF sample_counter = 9 THEN
                         sample_counter <= 0 ;
                         sample_val     <= '1';
                       ELSE
                         sample_counter <= sample_counter +1;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               WITH channel_counter SELECT
                 ADC_data_selected <= sample_reg(0) WHEN 0*2,
                                      sample_reg(1) WHEN 1*2,
                                      sample_reg(2) WHEN 2*2,
                                      sample_reg(3) WHEN 3*2,
                                      sample_reg(4) WHEN 4*2,
                                      sample_reg(5) WHEN 5*2,
                                      sample_reg(6) WHEN 6*2,
                                      sample_reg(7) WHEN OTHERS ;
-              ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) / 2);
+              ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
               sample <= sample_reg;
               --RHF1401_drvr_1: RHF1401_drvr
               --  GENERIC MAP (
               --    ChanelCount => ChanelCount)
               --  PORT MAP (
               --    cnv_clk    => cnv_sync,
               --    clk        => clk,
               --    rstn       => rstn,
               --    ADC_data   => ADC_data,
               --    --ADC_smpclk => OPEN,
               --    ADC_nOE    => ADC_nOE,
               --    sample     => sample,
               --    sample_val => sample_val);
             END ar_top_ad_conv_RHF1401;

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages